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Xilinx DS099 Spartan-3 FPGA Family data sheet
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Spartan-3 FPGA Family
Data Sheet
DS099 June 25, 2008
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Product Specification
This document includes all four modules of the Spartan ® -3 FPGA data sheet.
Module 1:
Spartan-3 FPGA Family: Introduction
and Ordering Information
DS099-1 (v2.4) June 25, 2008
Introduction
trs
Architectural Overview
Array Sizes and Resources
User I/O Chart
Ordering Information
Module 3:
Spartan-3 FPGA Family: DC and
Switching Characteristics
DS099-3 (v2.4) June 25, 2008
DC Electrical Characteristics
- Absolute Maximum Ratings
- Supply Voltage Specifications
- Recommended Operating Conditions
- DC Characteristics
Switching Characteristics
- I/O Timing
- Internal Logic Timing
- DCM Timing
- Configuration and JTAG Timing
Module 2:
Spartan-3 FPGA Family: Functional
Description
DS099-2 (v2.4) June 25, 2008
Input/Output Blocks (IOBs)
- IOB Overview
- SelectIO™ Interface I/O Standards
Configurable Logic Blocks (CLBs)
lk AM
Dedicated Multipliers
Digital Clock Manager (DCM)
Clock Network
Configuration
Module 4:
Spartan-3 FPGA Family: Pinout
Descriptions
DS099-4 (v2.4) June 25, 2008
Pin Descriptions
- Pin Behavior During Configuration
Package Overview
Pinout Tables
- trits
IMPORTANT NOTE: Each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy navigation
in this volume.
© 2003-2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm .
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS099 June 25, 2008
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Product Specification
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DS099 June 25, 2008
Product Specification
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Spartan-3 FPGA Family:
Introduction and Ordering
Information
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DS099-1 (v2.4) June 25, 2008
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Product Specification
Introduction
The Spartan ® -3 family of Field-Programmable Gate Arrays
is specifically designed to meet the needs of high volume,
cost-sensitive consumer electronic applications. The
eight-member family offers densities ranging from 50,000 to
five million system gates, as shown in Ta b l e 1 .
The Spartan-3 family builds on the success of the earlier
Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of
I/Os, and the overall level of performance as well as by
improving clock management functions. Numerous
enhancements derive from the Virtex ® -II platform technol-
ogy. These Spartan-3 FPGA enhancements, combined with
advanced process technology, deliver more functionality
and bandwidth per dollar than was previously possible, set-
ting new standards in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3 FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home network-
ing, display/projection and digital television equipment.
The Spartan-3 family is a superior alternative to mask pro-
grammed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
The Spartan-3 FPGAs are the first platform among several
Features
Low-cost, high-performance logic solution for high-volume,
consumer-oriented applications
- Densities up to 74,880 logic cells
SelectIO™ interface signaling
- Up to 633 I/O pins
- 622 Mb/s data transfer rate per I/O
- 18 single-ended signal standards
- 8 differential I/O standards including LVDS, RSDS
- Termination by Digitally Controlled Impedance
- Signal swing ranging from 1.14V to 3.465V
- Double Data Rate (DDR) support
- DDR, DDR2 SDRAM support up to 333 Mbps
ic r r s
- Abundant logic cells with shift register capability
- Wide, fast multiplexers
- Fast look-ahead carry logic
- Dedicated 18 x 18 multipliers
- JTAG logic compatible with IEEE 1149.1/1532
SelectRAM™ hierarchical memory
- Up to 1,872 Kbits of total block RAM
- Up to 520 Kbits of total distributed RAM
Digital Clock Manager (up to four DCMs)
- Clock skew elimination
- Frequency synthesis
- High resolution phase shifting
Eight global clock lines and abundant routing
Fully supported by Xilinx ISE ® and WebPACK ™
software development systems
MicroBlaze ™ and PicoBlaze ™ processor, PCI ® , PCI
Express ® PIPE Endpoint , and other IP cores
Pb-free packaging options
Automotive Spartan-3 XA Family variant
Table 1: Summary of Spartan-3 FPGA Attributes
Equivalent
Logic
Cells 1
CLB Array
(One CLB = Four Slices)
Distributed
RAM Bits
(K=1024)
Block RAM
Bits
(K=1024)
Maximum
Differential
I/O Pairs
Device
System
Gates
Rows Columns
Total
CLBs
Dedicated
Multipliers DCMs
Maximum
User I/O
XC3S50 2
50K
1,728
16
12
192
12K
72K
4
2
124
56
XC3S200 2
200K
4,320
24
20
480
30K
216K
12
4
173
76
XC3S400 2
400K
8,064
32
28
896
56K
288K
16
4
264
116
XC3S1000 2
1M
17,280
48
40
1,920
120K
432K
24
4
391
175
XC3S1500
1.5M
29,952
64
52
3,328
208K
576K
32
4
487
221
XC3S2000
2M
46,080
80
64
5,120
320K
720K
40
4
565
270
XC3S4000
4M
62,208
96
72
6,912
432K
1,728K
96
4
633
300
XC3S5000
5M
74,880
104
80
8,320
520K
1,872K
104
4
633
300
Notes:
1. Logic Cell = 4-input Look-Up Table (LUT) plus a ‘D’ flip-flop. "Equivalent Logic Cells" equals "Total CLBs" x 8 Logic Cells/CLB x 1.125 effectiveness.
2. These devices are available in Xilinx Automotive versions as described in DS314 : Spartan-3 Automotive XA FPGA Family.
© 2003-2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm .
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS099-1 (v2.4) June 25, 2008
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Product Specification
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Spartan-3 FPGA Family: Introduction and Ordering Information
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Architectural Overview
The Spartan-3 family architecture consists of five funda-
mental programmable functional elements:
Configurable Logic Blocks (CLBs) contain RAM-based
Look-Up Tables (LUTs) to implement logic and storage
elements that can be used as flip-flops or latches.
CLBs can be programmed to perform a wide variety of
logical functions as well as to store data.
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. Each IOB supports bidirectional data flow plus
3-state operation. Twenty-six different signal standards,
including eight high-performance differential standards,
are available as shown in Ta b l e 2 . Double Data-Rate
(DDR) registers are included. The Digitally Controlled
Impedance (DCI) feature provides automatic on-chip
terminations, simplifying board designs.
Block RAM provides data storage in the form of 18-Kbit
dual-port blocks.
Multiplier blocks accept two 18-bit binary numbers as
inputs and calculate the product.
Digital Clock Manager (DCM) blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase shifting clock
signals.
These elements are organized as shown in Figure 1 . A ring
of IOBs surrounds a regular array of CLBs. The XC3S50
has a single column of block RAM embedded in the array.
Those devices ranging from the XC3S200 to the XC3S2000
have two columns of block RAM. The XC3S4000 and
XC3S5000 devices have four RAM columns. Each column
is made up of several 18-Kbit RAM blocks; each block is
associated with a dedicated multiplier. The DCMs are posi-
tioned at the ends of the outer block RAM columns.
The Spartan-3 family features a rich network of traces and
switches that interconnect all five functional elements,
transmitting signals among them. Each functional element
has an associated switch matrix that permits multiple con-
nections to the routing.
DS099-1_01_032703
Notes:
1. The two additional block RAM columns of the XC3S4000 and XC3S5000
devices are shown with dashed lines. The XC3S50 has only the block RAM
column on the far left.
Figure 1: Spartan-3 Family Architecture
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Spartan-3 FPGA Family: Introduction and Ordering Information
Configuration
Spartan-3 FPGAs are programmed by loading configuration
data into robust, reprogrammable, static CMOS configura-
tion latches (CCLs) that collectively control all functional
elements and routing resources. Before powering on the
FPGA, configuration data is stored externally in a PROM or
some other nonvolatile medium either on or off the board.
After applying power, the configuration data is written to the
FPGA using any of five different modes: Master Parallel,
Slave Parallel, Master Serial, Slave Serial, and Boundary
Scan (JTAG). The Master and Slave Parallel modes use an
8-bit wide SelectMAP port.
The recommended memory for storing the configuration
data is the low-cost Xilinx Platform Flash PROM family,
which includes the XCF00S PROMs for serial configuration
and the higher density XCF00P PROMs for parallel or serial
configuration.
I/O Capabilities
The SelectIO feature of Spartan-3 devices supports 18 sin-
gle-ended standards and 8 differential standards as listed in
Ta b l e 2 . Many standards support the DCI feature, which
uses integrated terminations to eliminate unwanted signal
reflections..
Table 2: Signal Standards Supported by the Spartan-3 Family
Standard
Category
Description
V CCO
(V)
Class
Symbol
(IOSTANDARD)
DCI
Option
Single-Ended
GTL
Gunning Transceiver Logic
N/A
Terminated
GTL
Yes
Plus
GTLP
Yes
HSTL
High-Speed Transceiver Logic
1.5
I
HSTL_I
Yes
III
HSTL_III
Yes
1.8
I
HSTL_I_18
Yes
II
HSTL_II_18
Yes
III
HSTL_III_18
Yes
LVCMOS
Low-Voltage CMOS
1.2
N/A
LVCMOS12
No
1.5
N/A
LVCMOS15
Yes
1.8
N/A
LVCMOS18
Yes
2.5
N/A
LVCMOS25
Yes
3.3
N/A
LVCMOS33
Yes
LVTTL
Low-Voltage Transistor-Transistor Logic
3.3
N/A
LVTTL
No
PCI
Peripheral Component Interconnect
3.0
33 MHz (1)
PCI33_3
No
SSTL
Stub Series Terminated Logic
1.8
N/A ( ± 6.7 mA)
SSTL18_I
Yes
N/A ( ± 13.4 mA)
SSTL18_II
No
2.5
I
SSTL2_I
Yes
II
SSTL2_II
Yes
Differential
LDT
(ULVDS)
Lightning Data Transport (HyperTransport™)
Logic
2.5
N/A
LDT_25
No
LVDS
Low-Voltage Differential Signaling
Standard
LVDS_25
Yes
Bus
BLVDS_25
No
Extended Mode
LVDSEXT_25
Yes
LVPECL
Low-Voltage Positive Emitter-Coupled Logic
2.5
N/A
LVPECL_25
No
RSDS
Reduced-Swing Differential Signaling
2.5
N/A
RSDS_25
No
HSTL
Differential High-Speed Transceiver Logic
1.8
II
DIFF_HSTL_II_18
Yes
SSTL
Differential Stub Series Terminated Logic
2.5
II
DIFF_SSTL2_II
Yes
Notes:
1. 66 MHz PCI is not supported by the Xilinx IP core although PCI66_3 is an available I/O standard.
DS099-1 (v2.4) June 25, 2008
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Product Specification
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