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ISE 11 In-Depth Tutorial
ISE In-Depth
Tutorial
UG695 (v 11.2) June 24, 2009
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ISE 11 In-Depth Tutorial
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Preface
About This Tutorial
About the In-Depth Tutorial
This tutorial gives a description of the features and additions to Xilinx ® ISE™ 11. The
primary focus of this tutorial is to show the relationship among the design entry tools,
Xilinx and third-party tools, and the design implementation tools.
This guide is a learning tool for designers who are unfamiliar with the features of the ISE
software or those wanting to refresh their skills and knowledge.
You may choose to follow one of the three tutorial flows available in this document. For
information about the tutorial flows, see “Tutorial Flows.”
Tutorial Contents
This guide covers the following topics.
Chapter 1 , “Overview of ISE,” introduces you to the ISE primary user interface,
Project Navigator, and the synthesis tools available for your design.
Chapter 2 , “HDL-Based Design,” guides you through a typical HDL-based design
procedure using a design of a runner’s stopwatch. This chapter also shows how to use
ISE accessories such as CORE Generator™, and ISE Text Editor.
Chapter 3 , “Schematic-Based Design,” explains many different facets of a schematic-
based ISE design flow using a design of a runner’s stopwatch. This chapter also
shows how to use ISE accessories such as CORE Generator™, and ISE Text Editor.
Chapter 4 , “Behavioral Simulation,” explains how to simulate a design before design
implementation to verify that the logic that you have created is correct.
Chapter 5 , “Design Implementation,” describes how to Translate, Map, Place, Route,
and generate a Bit file for designs.
Chapter 6 , “Timing Simulation,” explains how to perform a timing simulation using
the block and routing delay information from the routed design to give an accurate
assessment of the behavior of the circuit under worst-case conditions.
Chapter 7 , “iMPACT Tutorial” explains how to program a device with a newly
created design using the IMPACT configuration tool.
ISE 11 In-Depth Tutorial
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Preface: About This Tutorial
Tutorial Flows
This document contains three tutorial flows. In this section, the three tutorial flows are
outlined and briefly described, in order to help you determine which sequence of chapters
applies to your needs. The tutorial flows include:
HDL Design Flow
Schematic Design Flow
Implementation-only Flow
HDL Design Flow
The HDL Design flow is as follows:
Chapter 2 , “HDL-Based Design”
Chapter 4 , “Behavioral Simulation”
Note that although behavioral simulation is optional, it is strongly recommended in
this tutorial flow.
Chapter 5 , “Design Implementation”
Chapter 6 , “Timing Simulation”
Note that although timing simulation is optional, it is strongly recommended in this
tutorial flow.
Chapter 7 , “iMPACT Tutorial”
Schematic Design Flow
The Schematic Design flow is as follows:
Chapter 3 , “Schematic-Based Design”
Chapter 4 , “Behavioral Simulation”
Note that although behavioral simulation is optional, it is strongly recommended in
this tutorial flow.
Chapter 5 , “Design Implementation”
Chapter 6 , “Timing Simulation”
Note that although timing simulation is optional, it is strongly recommended.
Chapter 7 , “iMPACT Tutorial”
Implementation-only Flow
The Implementation-only flow is as follows:
Chapter 5 , “Design Implementation”
Chapter 6 , “Timing Simulation”
Note that although timing simulation is optional, it is strongly recommended in this
tutorial flow.
Chapter 7 , “iMPACT Tutorial”
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Additional Resources
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Additional Resources
To find additional documentation, see the Xilinx website at:
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
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