ZXSpectrum128K_TechnicalManual.pdf

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Sinclair
Spectrum 128
Service
Manual
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SERVICING MANUAL
FOR
SPECTRUM 128 ©
LIST OF CONTENTS
SECTION 1
INTRODUCTION
SECTION 2
SYSTEM DESCRIPTION
SECTION 3
SETTING UP AND SYSTEM TEST
SECTION 4
FAULT FINDING AND REPAIR
SECTION 5
PARTS LISTS
LIST OF ILLUSTRATIONS
Fig No
Spectrum 128 Block Diagram
1.1
Uncontended RAM RAS7CAS Timing
1.2
Keyboard Upper Membrane
1.3
Keyboard Lower Membrane
1.4
Spectrum 128 Logic Circuit
1.5
System 128 Analogue Circuit
1.6
Keypad Circuit
1.7
Test Oscillograms
4.1
Spectrum 128 PCB Component Layout
5.1
Keypad PCB Component Layout
5.2
| Prepared by BRAVEMAY LTD
for SINCLAIR RESEARCH LTD
ti)
CD i A A A
SERVICE MANUAL 128
X-1223
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SECTION 1
SYSTEM DESCRIPTION
Sub-Section
LIST OF CONTENTS
Page No.
1
Introduction
1.1
2
Architecture
1.3
3
Z80A CPU
1.3
4
Memory Organisation
1.5
Read/Write Operations and Bus Arbitration
1.8
5
Input/Output
1.11
TV Picture Generation and Sound Output
1.11
Keyboard Scanning
.1.13
Tape Interface
1.16
Programmable Sound Generator
1.17
RS232C/MIDI Interface
1.18
Keypad Scanning
1.19
6
Power Supplies
1.22
Fig
ILLUSTRATIONS
1.1
Spectrum 128 Block_Dj_acjram
1.2
1.2
Uncontended RAM RAS/CAS Timing
1.10
1.3
Keyboard Upper Membrane
1.14
1.4
Keyboard Lower Membrane
1.15
1.5
Spectrum 128 Logic Circuit
1.23
1.6
Spectrum 128 Analogue Circuit
1.24
1.7
Keypad Circuit
1.25
1.
INTRODUCTION
1.1 The Spectrum 128 is a derivative of the 48K Spectrum Plus
offering 128K of RAM, music quality sound, greatly improved
video quality and higher hardware reliability.
1.2 The firmware is capable of running in Spectrum 48K mode or,
alternatively in 128K mode, which will support paged memory in
the form of a RAM disk. Extended BASIC to handle the sound
facility is provded, and a full screen editor is incorporated
in the firmware.
1.1
SR1AAA
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1.3
A list of the principle features appears below:
(a) 128K dynamic RAM
(b) 32K ROM
(c) Numeric keypad
(d) TV sound with composite video
(e) Elimination of dot crawl (single crystal operation)
(f) RGB output
(g) RS232 serial port
(h) Musical instrument digital interface (MIDI)
(j) Software compatible with all previous Spectrums
(k) Edge connector compatible with Spectrum.
2.
ARCHITECTURE
2.1 The architecture of the Spectrum 128 shown in Figure 1.1 is
typical of many microcomputer systems is that it comprises a
single microprocessor chip (in this instance a Z80A or u780), a
read only memory (ROM) a paged random access memory (RAM) and
an input-output section. The latter handles the keyboard
input, tape and TV display functions using the logic gate array
(ULA ICD, and the keypad input, sound and RS232/MIDI
interfaces using the sound generator circuit IC32.
2.2
The analogue circuits (not shown) generate the 17.7 MHz master
clock, and process the RGB colour monitor and sound signals.
The resultant outputs are suitable for use with colour (RGB) or
black and white monitors, and domestic UHF television
receivers. A modulated sound carrier is output with the
composite video.
2.3 The computer is built on a single printed circuit board which
also includes a regulated power supply fed from an external 9V
power pack. The keyboard matrix is part of the upper case
assembly and is connected to the board via two ribbon cables
KB1 and K82. A digital keypad is also provided, connected via
a flexible cable. It can be used as a games controller or
calculator pad and has special function keys for use with the
full screen editor. An in-built peripheral interface
controller (PIC) performs the keypad scanning routines and
delivers an output to the Z80 on demand.
3.
Z80A CPU
3.1
The Z80A is an 8-bit single chip central processing unit (CPU).
It is clocked at 3.5 MHz from a divide of an external source
controlled by the logic gate array (ULA) and has a standard
three bus input/output arrangement. These buses are the data
Bus, Address Bus and Control Bus respectively.
1.3
SR1AAA
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3.2 Data Bus. 07-00 constitutes an 8-bit bi-directional data bus
with active high, tri-state input/outputs. It is used for data
exchanges with the memory, sound chip and the ULA.
3.3
Address Bus. A15-AO constitutes a 16-bit address bus with
active high, tri-state outputs. The address bus provides the
address for memory data exchanges and for data exchanges with
the ULA. It is also used during the interrupt routine (see
below) when scanning the keyboard matrix.
3.4 Control Bus. The control bus is a collection of individual
signals which generally organise the flow of data on the
address and data buses. The block diagram only shows five of
these signals although others of minor importance are made
available at the expansion port (see Figure 1.5 for details).
3.5 Starting with memory request (MREQ), this signal is active low
indicating when the address bus holds a valid address for a
memory read or memory write operation. Input/Output request
(IORQ) is also active low but indicates when the address bus
holds a valid address for I/O read/write operations.
3.6 The read and write signals (RD and W) are active low, and one
or other is active indicating that the CPU wants to read or
write data to a memory location or I/O device. All the control
signals discussed so far are active low, tri-state outputs.
3.7 The last control signal described here is the maskable
interrupt (INT). This input is active low and is generated by
the ULA once every 20 ms. Each time it is received the CPU
'calls' the 'maskable interrupt' routine during which the
real-time clock is incremented and the keyboard and keypad
scanned.
3.8 CPU Clock. Returning to the CPU clock mentioned earlier in
this section, the ULA is able to inhibit this input bringing
the CPU to a temporary halt. This mechanism gives the ULA
absolute priority, allowing it to access the contended RAM
without interference from the CPU (see RAM description).
Switching transistor TR3 ensures that the clock amplitude is
+5V rather than some arbitrary TTL level. This is essential if
the CPU is to operate effectively while executing fast machine
code programs of the 'space invader' type.
3.9
Dynamic Memory Refresh. The CPU incorporates built-in dynamic
RAM refresh circuitry. As part of the instruction OP code
fetch cycle, the CPU performs a memory request after first
placing the refresh address on the lower eight bits of the
address bus. At the end of the cycle the address is
incremented so that over 255 fetch cycles, each row of the
dynamic RAM is refreshed.
1.4
SR1AAA
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