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C8051F120.book
Preliminary
C8051F120/1/2/3
C8051F124/5/6/7
High-Speed Mixed-Signal ISP FLASH MCU
ANALOG PERIPHERALS
-
SARADC
•
12-Bit (C8051F120/1/4/5)
•
10-Bit (C8051F122/3/6/7)
•
±1LSBINL
•
Programmable Throughput up to 100 ksps
•
Up to 8 External Inputs; Programmable as Single-Ended or
Differential
•
Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5
•
Data-Dependent Windowed Interrupt Generator
•
Built-in Temperature Sensor
-
8-bit ADC
•
Programmable Throughput up to 500 ksps
•
8 External Inputs (Single-Ended or Differential)
•
Programmable Amplifier Gain: 4, 2, 1, 0.5
-
Two 12-bit DACs
•
Can Synchronize Outputs to Timers for Jitter-Free Wave-
form Generation
-
TwoAnalogComparators
-
VoltageReference
-
VDD Monitor/Brown-Out Detector
ON-CHIP JTAG DEBUG & BOUNDARYSCAN
-
On-Chip Debug Circuitry Facilitates Full- Speed, Non-
Intrusive In-Circuit/In-System Debugging
-
Provides Breakpoints, Single-Stepping, Watchpoints,
Stack Monitor; Inspect/Modify Memory and Registers
-
Superior Performance to Emulation Systems Using ICE-
Chips, Target Pods, and Sockets
-
IEEE1149.1 Compliant Boundary Scan
-
Complete Development Kit
CCORE
-
Pipelined Instruction Architecture; Executes 70% of
Instruction Set in 1 or 2 System Clocks
-
Up to 100 MIPS (C8051F120/1/2/3) or 50 MIPS
(C8051F124/5/6/7) Throughput using Integrated PLL
-
2-cycle 16 x 16 MAC Engine (C8051F120/1/2/3)
-
Flexible Interrupt Sources
MEMORY
-
8448 Bytes Internal Data RAM (8k + 256)
-
128k Bytes Banked FLASH; In-System programmable in
1024-byte Sectors
-
External 64k Byte Data Memory Interface (programma-
ble multiplexed or non-multiplexed modes)
DIGITAL PERIPHERALS
-
8 Byte-Wide Port I/O (C8051F120/2/4/6); 5V tolerant
-
4 Byte-Wide Port I/O (C8051F121/3/5/7); 5V tolerant
-
Hardware SMBus™ (I
2
C™ Compatible), SPI™, and
Two UART Serial Ports Available Concurrently
-
Programmable 16-bit Counter/Timer Array with
6 Capture/Compare Modules
-
5 General Purpose 16-bit Counter/Timers
-
Dedicated Watch-Dog Timer; Bi-directional Reset Pin
CLOCK SOURCES
-
Internal Precision Oscillator: 24.5 MHz
-
Flexible PLL technology
-
External Oscillator: Crystal, RC, C, or Clock
POWER SUPPLIES
-
Supply Range: 2.7-3.6V (50 MIPS) 3.0-3.6V (100 MIPS)
-
Power Saving Sleep and Shutdown Modes
100-PINTQFP OR64-PINTQFP PACKAGING
-
Temperature Range: -40°C to +85°C
µ
ANALOG PERIPHERALS
DIGITAL I/O
TEMP
SENSOR
UART0
Port0
Port1
Port2
Port3
10/12-bit
100ksps
ADC
UART1
PGA
SMBus
SPI Bus
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
VREF
PGA
8-bit
500ksps
ADC
Port 4
Port 5
Port 6
Port 7
12-Bit
DAC
+
-
+
-
12-Bit
DAC
VOLTAGE
COMPARATORS
64 pin
100 pin
HIGH-SPEED CONTROLLER CORE
8051 CPU
(50 or 100MIPS)
128KB
ISP FLASH
8448 B
SRAM
16 x 16 MAC
('F120/1/2/3)
20
INTERRUPTS
DEBUG
CIRCUITRY
CLOCK / PLL
CIRCUIT
JTAG
DS008-1.1-JUN03
CYGNAL Integrated Products, Inc.
© 2003
Page 1
HIGHSPEED 8051
C8051F120/1/2/3
C8051F124/5/6/7
Preliminary
Notes
Page 2
DS008-1.1-JUN03
© 2003 Cygnal Integrated Products, Inc.
Preliminary
C8051F120/1/2/3
C8051F124/5/6/7
TABLE OF CONTENTS
1. SYSTEM OVERVIEW.........................................................................................................19
1.1. CIP-51™ Microcontroller Core ......................................................................................25
1.1.1. Fully 8051 Compatible ..........................................................................................25
1.1.2. Improved Throughput ............................................................................................25
1.1.3. Additional Features................................................................................................26
1.2. On-Chip Memory ............................................................................................................27
1.3. JTAG Debug and Boundary Scan ...................................................................................28
1.4. 16 x 16 MAC (Multiply and Accumulate) Engine..........................................................29
1.5. Programmable Digital I/O and Crossbar .........................................................................30
1.6. Programmable Counter Array .........................................................................................31
1.7. Serial Ports.......................................................................................................................32
1.8. 12-Bit Analog to Digital Converter.................................................................................33
1.9. 8-Bit Analog to Digital Converter...................................................................................34
1.10.Comparators and DACs...................................................................................................35
2. ABSOLUTE MAXIMUM RATINGS..................................................................................36
3. GLOBAL DC ELECTRICAL CHARACTERISTICS......................................................37
4. PINOUT AND PACKAGE DEFINITIONS........................................................................39
5. ADC0 (12-BIT ADC, C8051F120/1/4/5 ONLY)..................................................................49
5.1. Analog Multiplexer and PGA..........................................................................................49
5.2. ADC Modes of Operation ...............................................................................................51
5.2.1. Starting a Conversion.............................................................................................51
5.2.2. Tracking Modes .....................................................................................................52
5.2.3. Settling Time Requirements ..................................................................................53
5.3. ADC0 Programmable Window Detector.........................................................................60
6. ADC0 (10-BIT ADC, C8051F122/3/6/7 ONLY)..................................................................67
6.1. Analog Multiplexer and PGA..........................................................................................67
6.2. ADC Modes of Operation ...............................................................................................69
6.2.1. Starting a Conversion.............................................................................................69
6.2.2. Tracking Modes .....................................................................................................70
6.2.3. Settling Time Requirements ..................................................................................71
6.3. ADC0 Programmable Window Detector.........................................................................78
7. ADC2 (8-BIT ADC)...............................................................................................................85
7.1. Analog Multiplexer and PGA..........................................................................................85
7.2. ADC2 Modes of Operation .............................................................................................86
7.2.1. Starting a Conversion.............................................................................................86
7.2.2. Tracking Modes .....................................................................................................86
7.2.3. Settling Time Requirements ..................................................................................88
7.3. ADC2 Programmable Window Detector.........................................................................94
7.3.1. Window Detector In Single-Ended Mode .............................................................94
7.3.2. Window Detector In Differential Mode.................................................................95
8. DACS, 12-BIT VOLTAGE MODE......................................................................................99
8.1. DAC Output Scheduling..................................................................................................99
© 2003 Cygnal Integrated Products, Inc.
DS008-1.1-JUN03
Page 3
C8051F120/1/2/3
C8051F124/5/6/7
Preliminary
8.1.1. Update Output On-Demand ...................................................................................99
8.1.2. Update Output Based on Timer Overflow...........................................................100
8.2. DAC Output Scaling/Justification.................................................................................100
9. VOLTAGE REFERENCE (C8051F120/2/4/6) .................................................................107
10. VOLTAGE REFERENCE (C8051F121/3/5/7) .................................................................109
11. COMPARATORS................................................................................................................111
12. CIP-51 MICROCONTROLLER........................................................................................119
12.1.Instruction Set................................................................................................................120
12.1.1. Instruction and CPU Timing................................................................................120
12.1.2. MOVX Instruction and Program Memory...........................................................120
12.2.Memory Organization ...................................................................................................125
12.2.1. Program Memory.................................................................................................125
12.2.2. Data Memory .......................................................................................................127
12.2.3. General Purpose Registers ...................................................................................127
12.2.4. Bit Addressable Locations ...................................................................................127
12.2.5. Stack .................................................................................................................127
12.2.6. Special Function Registers...................................................................................128
12.2.6.1.SFR Paging..................................................................................................128
12.2.6.2.Interrupts and SFR Paging...........................................................................128
12.2.6.3.SFR Page Stack Example ............................................................................130
12.2.7. Register Descriptions ...........................................................................................143
12.3.Interrupt Handler ...........................................................................................................146
12.3.1. MCU Interrupt Sources and Vectors ...................................................................146
12.3.2. External Interrupts ...............................................................................................146
12.3.3. Interrupt Priorities................................................................................................148
12.3.4. Interrupt Latency..................................................................................................148
12.3.5. Interrupt Register Descriptions ............................................................................149
12.4.Power Management Modes ...........................................................................................155
12.4.1. Idle Mode.............................................................................................................155
12.4.2. Stop Mode............................................................................................................155
13. MULTIPLY AND ACCUMULATE (MAC0)...................................................................157
13.1.Special Function Registers ............................................................................................157
13.2.Integer and Fractional Math ..........................................................................................158
13.3.Operating in Multiply and Accumulate Mode...............................................................159
13.4.Operating in Multiply Only Mode.................................................................................159
13.5.Accumulator Shift Operations.......................................................................................159
13.6.Rounding and Saturation ...............................................................................................160
13.7.Usage Examples ............................................................................................................160
14. RESET SOURCES ..............................................................................................................167
14.1.Power-on Reset..............................................................................................................168
14.2.Power-fail Reset ............................................................................................................168
14.3.External Reset................................................................................................................168
14.4.Missing Clock Detector Reset .......................................................................................169
14.5.Comparator0 Reset ........................................................................................................169
14.6.External CNVSTR0 Pin Reset.......................................................................................169
Page 4
DS008-1.1-JUN03
© 2003 Cygnal Integrated Products, Inc.
Preliminary
C8051F120/1/2/3
C8051F124/5/6/7
14.7.Watchdog Timer Reset ..................................................................................................169
14.7.1. Enable/Reset WDT ..............................................................................................169
14.7.2. Disable WDT .......................................................................................................170
14.7.3. Disable WDT Lockout.........................................................................................170
14.7.4. Setting WDT Interval...........................................................................................170
15. OSCILLATORS...................................................................................................................173
15.1.Programmable Internal Oscillator .................................................................................173
15.2.External Oscillator Drive Circuit...................................................................................175
15.3.System Clock Selection.................................................................................................175
15.4.External Crystal Example..............................................................................................177
15.5.External RC Example ....................................................................................................177
15.6.External Capacitor Example..........................................................................................177
15.7.Phase-Locked Loop (PLL) ............................................................................................178
15.7.1. PLL Input Clock and Pre-divider.........................................................................178
15.7.2. PLL Multiplication and Output Clock .................................................................178
15.7.3. Powering on and Initializing the PLL..................................................................179
16. FLASH MEMORY..............................................................................................................185
16.1.Programming The Flash Memory .................................................................................185
16.1.1. Non-volatile Data Storage ...................................................................................185
16.1.2. Erasing FLASH Pages From Software ................................................................186
16.1.3. Writing FLASH Memory From Software ...........................................................187
16.2.Security Options ............................................................................................................188
17. BRANCH TARGET CACHE.............................................................................................193
17.1.Cache and Prefetch Operation .......................................................................................193
17.2.Cache and Prefetch Optimization..................................................................................194
18. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM.......................199
18.1.Accessing XRAM..........................................................................................................199
18.1.1. 16-Bit MOVX Example.......................................................................................199
18.1.2. 8-Bit MOVX Example.........................................................................................199
18.2.Configuring the External Memory Interface .................................................................199
18.3.Port Selection and Configuration ..................................................................................200
18.4.Multiplexed and Non-multiplexed Selection.................................................................202
18.4.1. Multiplexed Configuration ..................................................................................202
18.4.2. Non-multiplexed Configuration...........................................................................203
18.5.Memory Mode Selection ...............................................................................................204
18.5.1. Internal XRAM Only ...........................................................................................204
18.5.2. Split Mode without Bank Select ..........................................................................204
18.5.3. Split Mode with Bank Select ...............................................................................205
18.5.4. External Only.......................................................................................................205
18.6.Timing .......................................................................................................................206
18.6.1. Non-multiplexed Mode........................................................................................207
18.6.1.1.16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’................................207
18.6.1.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’............208
18.6.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’...............................209
18.6.2. Multiplexed Mode................................................................................................210
© 2003 Cygnal Integrated Products, Inc.
DS008-1.1-JUN03
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