ICH5_5R.pdf

Intel ® 82801EB I/O Controller

Hub 5 (ICH5) / Intel ® 82801ER

I/O Controller Hub 5 R (ICH5R)

Datasheet

April 2003

Document Number: 252516-001

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL ® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel ® 82801EB I/O Controller Hub 5 (ICH5) / Intel ® 82801ER I/O Controller Hub 5 R (ICH5R) chipset component may contain design defects or

errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

I 2 C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I 2 C bus/protocol and was developed by Intel.

Implementations of the I 2 C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips

Corporation.

Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.

Intel, Intel SpeedStep and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other

countries.

*Other names and brands may be claimed as the property of others.

Intel ® 82801EB ICH5 / 82801ER ICH5R Datasheet

Contents

Intel ® ICH5/ICH5R Features

PCI Bus Interface

— New: Supports PCI Revision 2.3 Specification at

33 MHz

— 6 available PCI REQ/GNT pairs

— One PCI REQ/GNT pair can be given higher

arbitration priority (intended for external 1394

host controller)

— Support for 44-bit addressing on PCI using DAC

protocol

New: Integrated 1.5 V Voltage Regulator (INTVR) for

the Suspend wells

Power Management Logic

— New: ACPI 2.0 compliant

— ACPI-defined power states (C1, S3–S5)

— ACPI Power Management Timer

— PCI PME# support

— SMI# generation

— All registers readable/restorable for proper resume

from 0 V suspend states

— Support for APM-based legacy power

management for non-ACPI implementations

Integrated LAN Controller

— New: Integrated ASF Management Controller

— WfM 2.0 and IEEE 802.3 Compliant

— LAN Connect Interface (LCI)

— 10/100 Mbit/sec Ethernet Support

External Glue Integration

— Integrated Pull-up, Pull-down and Series

Termination resistors on IDE, processor I/F

— Integrated Pull-down and Series resistors on USB

New: Integrated Serial ATA Host Controllers

— Independent DMA operation on two ports.

— Data transfer rates up to 1.5 Gb/s (150 MB/s).

— RAID Level 0 Support (ICH5R Only)

Flash BIOS I/F supports BIOS Memory size up to

8 Mbytes

Low Pin Count (LPC) I/F

— Supports two Master/DMA devices.

— Support for Security Devices connected to LPC.

Integrated IDE Controller

— Supports “Native Mode” Register and Interrupts

— Independent timing of up to 4 drives

— Ultra ATA/100/66/33, BMIDE and PIO modes

— Tri-state modes to enable swap bay

Enhanced DMA Controller

— Two cascaded 8237 DMA controllers

— PCI DMA: Supports PC/PCI — Includes two

PC/PCI REQ#/GNT# pairs

— Supports LPC DMA

— Supports DMA Collection Buffer to provide Type-

F DMA performance for all DMA channels

USB 2.0

— New: Includes 4 UHCI Host Controllers,

increasing the number of external ports to eight

— Includes 1 EHCI Host Controller that supports all

eight ports

— Includes 1 USB 2.0 high-speed debug port

— Supports wake-up from sleeping states S1–S5

— Supports legacy Keyboard/Mouse software

Real-Time Clock

— 256-byte battery-backed CMOS RAM

— Integrated oscillator components

— Lower Power DC/DC Converter implementation

AC-Link for Audio and Telephony Codecs

— Support for 3 AC ‘97 2.3 codecs.

— Independent bus master logic for 8 channels (PCM

In/Out, PCM2 In, Mic 1 Input, Mic 2 Input,

Modem In/Out, S/PDIF Out)

— Support for up to six channels of PCM audio

output (full AC3 decode)

— Supports wake-up events

System TCO Reduction Circuits

— Timers to generate SMI# and Reset upon detection

of system hang

— Timers to detect improper processor reset

— Integrated processor frequency strap logic

— Supports ability to disable external devices

SMBus

— New: Provides independent manageability bus

through SMLink interface.

— Supports SMBus 2.0 Specification

— Host interface allows processor to communicate

via SMBus

— Slave interface allows an internal or external

Microcontroller to access system resources

— Compatible with most 2-Wire components that are

also I 2 C compatible

Interrupt Controller

— Supports up to 8 PCI interrupt pins

— Supports PCI 2.3 Message Signaled Interrupts

— Two cascaded 82C59 with 15 interrupts

— Integrated I/O APIC capability with 24 interrupts

— Supports Front Side Bus interrupt delivery

High-Precision Event Timers

— Advanced operating system interrupt scheduling

New: 1.5 V operation with 3.3 V I/O

— 5V tolerant buffers on IDE, PCI, USB Over-

current and Legacy signals

GPIO

— TTL, Open-Drain, Inversion

Package 31x31 mm 460 mBGA

Timers Based on 82C54

— System timer, Refresh request, Speaker tone

output

The Intel ® ICH5 / ICH5R may contain design defects or errors known as errata which may cause the products to deviate from

published specifications. Current characterized errata are available on request.

Intel ® 82801EB ICH5 / 82801ER ICH5R Datasheet

Contents

System Block Diagram

Processor

MCH

AGP

USB 2.0

(Supports 8 USB ports)

Power Management

IDE-Primary

Clock Generators

Intel ® 82801EB

ICH5

Intel ® 82801ER

ICH5R

IDE-Secondary

System Management

(TCO)

SATA (2 ports)

SMBus 2.0/I 2 C

AC’97 Codec(s)

PCI Bus

LAN Connect

LAN

GPIO

...

LPC I/F

Super I/O

Other ASICs

(Optional)

Flash BIOS

Intel ® 82801EB ICH5 / 82801ER ICH5R Datasheet

Contents

Introduction .................................................................................................................................. 39

1.1

About This Manual.............................................................................................................. 39

1.2

Overview ............................................................................................................................. 42

Signal Description ....................................................................................................................... 49

2.1

Hub Interface to Host Controller .........................................................................................51

2.2

Link to LAN Connect ........................................................................................................... 51

2.3

EEPROM Interface .............................................................................................................51

2.4

Flash BIOS Interface .......................................................................................................... 52

2.5

PCI Interface ....................................................................................................................... 52

2.6

Serial ATA Interface............................................................................................................54

2.7

IDE Interface ....................................................................................................................... 55

2.8

LPC Interface ...................................................................................................................... 56

2.9

Interrupt Interface ............................................................................................................... 57

2.10

USB Interface ..................................................................................................................... 58

2.11

Power Management Interface............................................................................................. 59

2.12

Processor Interface............................................................................................................. 60

2.13

SMBus Interface ................................................................................................................. 61

2.14

System Management Interface ........................................................................................... 61

2.15

Real Time Clock Interface ..................................................................................................62

2.16

Other Clocks ....................................................................................................................... 62

2.17

Miscellaneous Signals ........................................................................................................ 62

2.18

AC-Link ............................................................................................................................... 63

2.19

General Purpose I/O ........................................................................................................... 63

2.20

Power and Ground.............................................................................................................. 65

2.21

Pin Straps ........................................................................................................................... 66

2.21.1

Functional Straps ................................................................................................... 66

2.21.2

External RTC Circuitry ........................................................................................... 67

2.21.3

Power Sequencing Requirements ......................................................................... 67

2.21.3.1

V5REF / Vcc3_3 Sequencing Requirements ......................................... 67

2.21.3.2

3.3 V/1.5 V Standby Power Sequencing Requirements ........................68

2.21.4

Test Signals ........................................................................................................... 68

2.21.4.1

Test Mode Selection .............................................................................. 68

I tel ® ICH5 Power Planes and Pin States ..................................................................................69

3.1

Power Planes...................................................................................................................... 69

3.2

Integrated Pull-Ups and Pull-Downs ................................................................................... 70

3.3

IDE Integrated Series Termination Resistors .....................................................................71

3.4

Output and I/O Signals Planes and States ......................................................................... 71

3.5

Power Planes for Input Signals........................................................................................... 75

I tel ® ICH5 and System Clock Domains .................................................................................... 77

Functional Description ................................................................................................................ 79

5.1

Hub Interface to PCI Bridge (D30:F0)................................................................................. 79

5.1.1

PCI Bus Interface................................................................................................... 79

5.1.2

PCI-to-PCI Bridge Model ....................................................................................... 80

Intel ® 82801EB ICH5 / 82801ER ICH5R Datasheet

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika: