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W83697HF
WINBOND I/O
W83697HF Data Sheet Revision History
Version
on Web
Pages
Dates
Version
Main Contents
First published.
For Beta Site customers only
1
n.a.
08/23/99
0.40
2
98, 107, 116
11/15/99
0.41
H/W monitor register correction
3
4
5
6
7
8
9
1
0
Please note that all data and specifications are subject to change without notice. All
the trade marks of products and companies mentioned in this data sheet belong to
their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or
systems where malfunction of these products can reasonably be expected to result
in personal injury. Winbond customers using or selling these products for use in such
applications do so at their own risk and agree to fully indemnify Winbond for any
damages resulting from such improper use or sales.
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W83697HF
PRELIMINARY
1
PIN DESCRIPTION.............................................................................................................7
1.1 LPC INTERFACE .................................................................................................................................................. 7
1.2 FDC INTERFACE.................................................................................................................................................. 8
1.3 MULTI-MODE PARALLEL PORT ..................................................................................................................... 9
1.4 SERIAL PORT INTERFACE.............................................................................................................................. 14
1.5 INFRARED PORT ............................................................................................................................................... 15
1.6 FRESH ROM INTERFACE ................................................................................................................................ 15
1.7 HARDWARE MONITOR INTERFACE ........................................................................................................... 15
1.8 GAME PORT & MIDI PORT ............................................................................................................................. 17
1.9 POWER PINS ....................................................................................................................................................... 18
2
LPC (LOW PIN COUNT) INTERFACE.........................................................................19
3
FDC FUNCTIONAL DESCRIPTION .............................................................................20
3.1 W83697HF FDC................................................................................................................................................... 20
3.1.1 AT interface .................................................................................................................................................... 20
3.1.2 FIFO (Data) ................................................................................................................................................... 20
3.1.3 Data Separator .............................................................................................................................................. 21
3.1.4 Write Precompensation ................................................................................................................................. 21
3.1.5 FDC Core ....................................................................................................................................................... 22
3.1.6 FDC Commands ............................................................................................................................................ 22
3.2 REGISTER DESCRIPTIONS ............................................................................................................................. 34
3.2.1 Status Register A (SA Register) (Read base address + 0) .......................................................................... 34
3.2.2 Status Register B (SB Register) (Read base address + 1) .......................................................................... 36
3.2.3 Digital Output Register (DO Register) (Write base address + 2).............................................................. 38
3.2.4 Tape Drive Register (TD Register) (Read base address + 3)..................................................................... 38
3.2.5 Main Status Register (MS Register) (Read base address + 4) ................................................................... 39
3.2.6 Data Rate Register (DR Register) (Write base address + 4) ...................................................................... 39
3.2.7 FIFO Register (R/W base address + 5)........................................................................................................ 41
3.2.8 Digital Input Register (DI Register) (Read base address + 7)................................................................... 43
3.2.9 Configuration Control Register (CC Register) (Write base address + 7)................................................. 44
4
UART PORT.........................................................................................................................45
Publication Release Date: Aug 1999
- 1 -
Revision 0.40
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W83697HF
PRELIMINARY
4.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B) ........................... 45
4.2 REGISTER ADDRESS........................................................................................................................................ 45
4.2.1 UART Control Register (UCR) (Read/Write) .............................................................................................. 45
4.2.2 UART Status Register (USR) (Read/Write).................................................................................................. 48
4.2.3 Handshake Control Register (HCR) (Read/Write)...................................................................................... 50
4.2.4 Handshake Status Register (HSR) (Read/Write) ......................................................................................... 51
4.2.5 UART FIFO Control Register (UFR) (Write only)...................................................................................... 52
4.2.6 Interrupt Status Register (ISR) (Read only)................................................................................................. 53
4.2.7 Interrupt Control Register (ICR) (Read/Write)............................................................................................ 54
4.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) ....................................................................... 54
4.2.9 User-defined Register (UDR) (Read/Write) ................................................................................................. 55
5
CIR RECEIVER PORT......................................................................................................56
5.1 CIR REGISTERS.................................................................................................................................................. 56
5.1.1 Bank0.Reg0 - Receiver Buffer Registers (RBR) (Read) .............................................................................. 56
5.1.2 Bank0.Reg1 - Interrupt Control Register (ICR) .......................................................................................... 56
5.1.3 Bank0.Reg2 - Interrupt Status Register (ISR) ............................................................................................. 56
5.1.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) ...................... 57
5.1.5 Bank0.Reg4 - CIR Control Register (CTR) ................................................................................................. 57
5.1.6 Bank0.Reg5 - UART Line Status Register (USR)....................................................................................... 58
5.1.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG) .................................................................... 59
5.1.8 Bank0.Reg7 - User Defined Register (UDR/AUDR) .................................................................................. 61
5.1.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL).............................................................................. 62
5.1.10 Bank1.Reg2 - Version ID Regiister I (VID)............................................................................................... 63
5.1.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) .................... 63
5.1.12 Bank1.Reg4 - Timer Low Byte Register (TMRL) ...................................................................................... 63
5.1.13 Bank1.Reg5 - Timer High Byte Register (TMRH) .................................................................................... 63
6
PARALLEL PORT.............................................................................................................64
6.1 PRINTER INTERFACE LOGIC......................................................................................................................... 64
6.2 ENHANCED PARALLEL PORT (EPP)............................................................................................................ 65
6.2.1 Data Swapper ................................................................................................................................................ 65
6.2.2 Printer Status Buffer...................................................................................................................................... 66
6.2.3 Printer Control Latch and Printer Control Swapper ................................................................................. 67
6.2.4 EPP Address Port .......................................................................................................................................... 67
6.2.5 EPP Data Port 0-3 ........................................................................................................................................ 68
Publication Release Date: Aug 1999
Revision 0.40
926833890.022.png 926833890.023.png
W83697HF
PRELIMINARY
6.2.6 Bit Map of Parallel Port and EPP Registers ............................................................................................... 68
6.2.7 EPP Pin Descriptions .................................................................................................................................... 69
6.2.8 EPP Operation............................................................................................................................................... 69
6.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT............................................................................... 70
6.3.1 ECP Register and Mode Definitions ............................................................................................................ 70
6.3.2 Data and ecpAFifo Port................................................................................................................................ 71
6.3.3 Device Status Register (DSR)........................................................................................................................ 71
6.3.4 Device Control Register (DCR) .................................................................................................................... 72
6.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 ............................................................................................ 73
6.3.6 ecpDFifo (ECP Data FIFO) Mode = 011 ................................................................................................... 73
6.3.7 tFifo (Test FIFO Mode) Mode = 110........................................................................................................... 73
6.3.8 cnfgA (Configuration Register A) Mode = 111 .......................................................................................... 73
6.3.9 cnfgB (Configuration Register B) Mode = 111 .......................................................................................... 73
6.3.10 ecr (Extended Control Register) Mode = all ............................................................................................. 74
6.3.11 Bit Map of ECP Port Registers................................................................................................................... 75
6.3.12 ECP Pin Descriptions ................................................................................................................................. 76
6.3.13 ECP Operation ............................................................................................................................................ 77
6.3.14 FIFO Operation........................................................................................................................................... 77
6.3.15 DMA Transfers ............................................................................................................................................ 78
6.3.16 Programmed I/O (NON-DMA) Mode ........................................................................................................ 78
6.4 EXTENSION FDD MODE (EXTFDD)............................................................................................................. 78
6.5 EXTENSION 2FDD MODE (EXT2FDD) ........................................................................................................ 78
7
GENERAL PURPOSE I/O.................................................................................................79
8
ACPI REGISTERS FEATURES ......................................................................................82
9
HARDWARE MONITOR..................................................................................................83
9.1 GENERAL DESCRIPTION ................................................................................................................................ 83
9.2 ACCESS INTERFACE ........................................................................................................................................ 83
9.2.1 LPC interface ................................................................................................................................................. 83
9.3 ANALOG INPUTS............................................................................................................................................... 85
9.3.1 Monitor over 4.096V voltage: ...................................................................................................................... 85
9.3.2 Monitor negative voltage:............................................................................................................................. 85
9.3.3 Temperature Measurement Machine ........................................................................................................... 86
9.4 FAN SPEED COUNT AND FAN SPEED CONTROL ................................................................................... 87
Publication Release Date: Aug 1999
Revision 0.40
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