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L15: VLSI Integration and Performance
Transformations
Transformations
Acknowledgement:
Materials in this lecture are courtesy of the following sources and are used with permission.
Curt Schurgers
J. Rabaey, A. Chandrakasan, B. Nikolic. Digital Integrated Circuits: A Design Perspective.
Prentice Hall/Pearson, 2003.
L15: 6.111 Spring 2006
Introductory Digital Systems Laboratory
1
L15: VLSI Integration and Performance
 
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Layout 101
3-D Cross-Section
VDD
p-type substrate
n-type well
metal/pdiff
contact
SiO 2
SiO 2
W p
n +
n +
+
p +
p +
p +
n +
p
n
L p
N-channel MOSFET
P-channel MOSFET
IN
OUT
V DD
Figure by MIT OpenCourseWare.
W n
S
L n
contact
frommetal
to ndiff
G
Circuit Representation
GND
D
metal
poly
n+
diff
p+
diff
IN
OUT
Layout
D
Used with permission.
G
Follow simple design rules (contract
between process and circuit designers)
S
L15: 6.111 Spring 2006
Introductory Digital Systems Laboratory
2
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Custom Design/Layout
Itanium has 6 integer execution units like this
a
g64
CARRYGEN
node1
sum
ck1
sumb
to Cache
SUMGEN
+ LU
s0
b
s1
1000um
LU : Logical
Unit
From register files / Cache / Bypass
Multiplexers
Shifter
Adder stage 1
Wiring
Adder stage 2
Die photograph of the
Wiring
Itanium integer datapath
datapath
Courtesy Intel, as reprinted in Rabaey, et al. "Digital Integrated Circuits".
Adder stage 3
Sum Select
Bit- slice Design Methodology
slice Design Methodology
To register files / Cache
Hand crafting the layout to achieve maximum clock rates (> 1Ghz)
Exploits regularity in datapath structure to optimize interconnects
L15: 6.111 Spring 2006
Introductory Digital Systems Laboratory
3
Itanium integer
Bit
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The ASIC Approach
Design Capture
Behavioral
Verilog (or VHDL )
Pre-Layout
Simulation
Pre-Layout
Simulation
Structural
Logic Synthesis
Logic Synthesis
Floorplanning
Post-Layout
Simulation
Post-Layout
Simulation
Placement
Physical
Circuit
Extraction
Routing
Tape-out
Most Common Design Approach for Designs up to 500Mhz
Clock Rates
L15: 6.111 Spring 2006
Introductory Digital Systems Laboratory
4
Verilog (or VHDL )
Floorplanning
Placement
Circuit
Extraction
Routing
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Standard Cell Example
Power Supply Line (V DD )
Delay in (ns)!!
3-input NAND cell
(from ST Microelectronics):
C = Load capacitance
T = input rise/fall time
Ground Supply Line (GND)
Each library cell (FF, NAND, NOR, INV, etc.) and the variations on size
(strength of the gate) is fully characterized across temperature, loading, etc.
L15: 6.111 Spring 2006
Introductory Digital Systems Laboratory
5
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