ESDA18-1F2.pdf

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®
ESDA18-1F2
ASD
(Application Specific Devices)
TRANSIL™: Transient Voltage Suppressor
FEATURES AND BENEFITS:
Stand-off voltage 16V
Unidirectional device
Low clamping factor V CL /V BR
Fast response time
Very thin package: 0.65 mm
DESCRIPTION
The ESDA18-1F2 is a single line Transil diode
designed specifically for the protection of
integrated circuits into portable equipment and
miniaturized electronics devices subject to ESD &
EOS transient overvoltages.
Flip-Chip
(4 Bumps)
Table 1: Order Code
Part Number
Marking
ESDA18-1F2
EE
COMPLIES WITH THE FOLLOWING STANDARDS:
IEC61000-4-2
Level 4
Figure 1: Pin Configuration (ball side)
15kV (air discharge)
8kV (contact discharge)
A
B
1
K
A
2
K
A
K
A
TM: TRANSIL is a trademark of STMicroelectronics.
May 2005
REV. 1
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ESDA18-1F2
Table 2: Absolute Ratings (limiting value, per diode)
Symbol
Parameter and test conditions
Value
Unit
Peak pulse power dissipation
10 / 1000 µs pulse
100
P PP
T j initial = T amb
W
Peak pulse power dissipation
8 / 20 µs pulse
700
I FSM
Non repetitive surge peak forward current
t p =10 ms
T j initial = T amb
8
A
T j
Maximum operating junction temperature
125
°C
T stg
Storage temperature range
- 65 to + 175
°C
Table 3: Electrical Characteristics (T amb = 25°C )
Symbol
Parameter
I
V BR Breakdown voltage
I F
I RM
Leakage current
V RM Stand-off voltage
V F
V CL V BR V RM
V
V CL
Clamping voltage
I RM
R d
Dynamic impedance
I PP
Peak pulse current
Slope: 1/R d
I PP
C
Capacitance
V BR
I R
I RM V RM V CL I PP (1)
V F (2)
α
T
C
Part Number
min. max.
max.
max.
max.
max.
typ.
I F = 850mA
V R =0V
V
V
A
µA
V
V
A
V
10 -4 /°C
pF
ESDA18-1F2
16
18
1
0.5
10
20
1
1.3
8.5
230
(1) 8 / 20 µs pulse waveform.
(2) DC current not recommended for more than 5 sec. Even if Transil failure mode is short circuit the bumps could exceed melting temper-
ature and the component disassembled from the board.
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ESDA18-1F2
Figure 2: Relative variation of peak pulse
power versus initial junction temperature
Figure 3: Peak pulse power versus exponen-
tial pulse duration
P [T initial] / P [T initial=25°C)
PP j
PP j
P (W)
PP
1.1
10000
1.0
T initial=25°C
j
0.9
0.8
0.7
1000
0.6
0.5
0.4
100
0.3
0.2
0.1
T (°C)
j
t (µs)
p
0.0
10
0
25
50
75
100
125
150
1
10
100
1000
Figure 4: Clamping voltage versus peak pulse
current (typical values, exponential waveform)
Figure 5: Forward voltage drop versus peak
forward current (typical values)
I (A)
PP
I (A)
FM
100.0
1.E+01
8/20µs
T initial=25°C
j
1.E+00
T =125°C
j
10.0
T =25°C
j
1.E-01
1.0
1.E-02
V (V)
CL
V (V)
FM
0.1
1.E-03
10
12
14
16
18
20
22
24
26
28
30
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Figure 6: Junction capacitance versus reverse
voltage applied (typical values)
Figure 7: Relative variation of leakage current
versus junction temperature (typical values)
C(pF)
I [T ] / I [T =25°C]
Rj Rj
300
100
F=1MHz
V =30mV
T =25°C
V =10V
R
OSC
RMS
250
j
200
150
10
100
50
V (V)
R
T (°C)
j
0
1
0
1
2 3
4 5
6
7
8 9 10 11 12 13 14 15 16
25
50
75
100
125
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ESDA18-1F2
One major point is that the ESDA18-1F2 has to ensure the safety during reverse battery operation. Indeed,
during this operation the device must clamp the DC reverse voltage below 1.3V @ 0.85A (max current).
Thus reverse battery operation has been simulated by inverting the polatrity of the TRANSIL (please see
figures 8 and 9)
Figure 8: Reverse battery operation setup
PTC
Equivalent
mobile phone
impedance
V mains
I
V
4.7k
1nF
ESDA18-1F2
Figure 9: Reverse battery operation results
A short calculation based on Reverse battery operation results figures clearly show that in such real phone
application the ESDA18-1F2 clamp the DC voltage below 1.3V.
Typically the ESDA18-1F2 can clamp the DC voltage @ 0.9V @0.76A DC current:
V DC
=
2V max
----------------- 0.9V
Π
I DC
=
2 max
----------------- 0.76A
3.14
Π
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×
3.14
-----------------------
21.4
×
---------------------
21.2
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ESDA18-1F2
Figure 10: Ordering Information Scheme
ESDA 18 - 1 Fx
ESD Array
Breakdown Voltage
18 = 18 Volts max.
Number of line
1 = signle line
Package
F = Flip-Chip
x = 2: Leadfree Pitch = 500µm, Bump = 315µm
Figure 11: FLIP-CHIP Package Mechanical Data
500µm ± 50
315µm ± 50
650µm ± 65
0.95mm ± 50µm
Figure 12: Foot Print Recommendations
Figure 13: Marking
Dot, ST logo
xx = marking
yww = datecode
(y = year
ww = week)
365
240
Copper pad Diameter :
250µm recommended , 300µm max
z = packaging location
E
Solder stencil opening : 330µm
x
y
x
w
z
w
Solder mask opening recommendation :
340µm min for 315µm copper pad diameter
All dimensions in µm
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