ADuC845-7-8_A.pdf

MicroConverter ® Multichannel

24-/16-Bit ADCs with Embedded 62 kB

Flash and Single-Cycle MCU

ADuC845/ADuC847/ADuC848

FEATURES

High resolution Σ-∆ ADCs

Two independent 24-bit ADCs on the ADuC845

Single 24-bit ADC on the ADuC847 and

single 16-bit ADC on the ADuC848

Up to 10 ADC input channels on all parts

24-bit no missing codes

22-bit rms (19.5 bit p-p) effective resolution

Offset drift 10 nV/°C, gain drift 0.5 ppm/°C chop enabled

Power

Normal: 4.8 mA max @ 3.6 V (core CLK = 1.57 MHz)

Power-down: 20 µA max with wake-up timer running

Specified for 3 V and 5 V operation

Package and temperature range:

52-lead MQFP (14 mm × 14 mm), −40°C to +125°C

56-lead CSP (8 mm × 8 mm), −40°C to +85°C

APPLICATIONS

Multichannel sensor monitoring

Industrial/environmental instrumentation

Weigh scales, pressure sensors, temperature monitoring

Portable instrumentation, battery-powered systems

Data logging, precision system monitoring

Memory

62-kbyte on-chip Flash/EE program memory

4-kbyte on-chip Flash/EE data memory

Flash/EE, 100 year retention, 100 kcycle endurance

3 levels of Flash/EE program memory security

In-circuit serial download (no external hardware)

High speed user download (5 seconds)

2304 bytes on-chip data RAM

FUNCTIONAL BLOCK DIAGRAM

AV DD

ADuC845

8051-based core

8051-compatible instruction set

High performance single-cycle core

32 kHz external crystal

On-chip programmable PLL (12.58 MHz max)

3 × 16-bit timer/counter

24 programmable I/O lines, plus 8 analog or

digital input lines

11 interrupt sources, two priority levels

Dual data pointer, extended 11-bit stack pointer

AVCO

CURRENT

SOURCE

IEXC1

IEXC2

AIN0

BUF

PGA

PRIMARY

24-BIT Σ - ∆ ADC

12-BIT

DAC

BUF

DAC

MUX

AIN9

AINCOM

AGND

DUAL 16-BIT

Σ - ∆ DAC

AUXILIARY

24-BIT Σ - ∆ ADC

PWM0

MUX

REFIN2+

TEMP

SENSOR

DUAL 16-BIT

PWM

PWM1

REFIN2–

REFIN–

EXTERNAL

V REF

DETECT

INTERNAL

BAND GAP

V REF

REFIN+

SINGLE-CYCLE 8061 BASED MCU

On-chip peripherals

Internal power-on reset circuit

12-bit voltage output DAC

Dual 16-bit Σ-∆ DACs

On-chip temperature sensor (ADuC845 only)

Dual excitation current sources (200 µA)

Time interval counter (wake-up/RTC timer)

UART, SPI®, and I 2 C® serial I/O

High speed dedicated baud rate generator (incl 115,200)

Watchdog timer (WDT)

Power supply monitor (PSM)

RESET

DV DD

DGND

POR

62 kBYTES FLASH/EE PROGRAM MEMORY

4 kBYTES FLASH/EE DATA MEMORY

2304 BYTES USER RAM

3 × 16 BIT TIMERS

BAUD RATE TIMER

4 × PARALLEL

PORTS

PLL AND PRG

CLOCK DIV

POWER SUPPLY MON

WATCHDOG TIMER

UART, SPI, AND I 2 C

SERIAL I/O

OSC

WAKE-UP/

RTC TIMER

XTAL1

XTAL2

Figure 1. ADuC845 Functional Block Diagram

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.326.8703

ADuC845/ADuC847/ADuC848

TABLE OF CONTENTS

Specifications..................................................................................... 4

Abosolute Maximum Ratings ....................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

ADC SFR Interface..................................................................... 39

ADCSTAT (ADC Status Register) ........................................... 40

ADCMODE (ADC Mode Register)......................................... 41

ADC0CON1 (Primary ADC Control Register)..................... 43

General Description ....................................................................... 15

8052 Instruction Set ................................................................... 18

Timer Operation......................................................................... 18

ALE............................................................................................... 18

External Memory Access ........................................................... 18

Complete SFR Map .................................................................... 19

Functional Description .................................................................. 20

ADC0CON2 (Primary ADC Channel Select Register) ........ 44

SF (ADC Sinc Filter Control Register) .................................... 46

ICON (Excitation Current Sources Control Register) .......... 47

Nonvolatile Flash/EE Memory Overview ............................... 48

Flash/EE Program Memory ...................................................... 49

User Download Mode (ULOAD)............................................. 50

Using Flash/EE Data Memory .................................................. 51

8051 Instruction Set ................................................................... 20

Memory Organization ............................................................... 22

Special Function Registers (SFRs)............................................ 24

ADC Circuit Information.......................................................... 26

Auxiliary ADC (ADuC845 Only) ............................................ 32

Reference Inputs ......................................................................... 32

Burnout Current Sources .......................................................... 32

Reference Detect Circuit ........................................................... 33

Flash/EE Memory Timing ........................................................ 52

DAC Circuit Information.......................................................... 53

Pulse-Width Modulator (PWM).............................................. 55

On-Chip PLL (PLLCON).......................................................... 60

I 2 C Serial Interface ..................................................................... 61

SPI Serial Interface ..................................................................... 64

Using the SPI Interface .............................................................. 66

Dual Data Pointers ..................................................................... 67

Sinc Filter Register (SF) ............................................................. 33

Σ- ∆ Modulator ............................................................................ 33

Digital Filter ................................................................................ 33

ADC Chopping ........................................................................... 34

Calibration................................................................................... 34

Programmable Gain Amplifier ................................................. 35

Power Supply Monitor ............................................................... 68

Watchdog Timer ......................................................................... 69

Time Interval Counter (TIC).................................................... 70

8052 Compatible On-Chip Peripherals................................... 73

Timers/Counters ........................................................................ 75

UART Serial Interface................................................................ 80

Interrupt System ......................................................................... 85

Interrupt Priority........................................................................ 86

Bipolar/Unipolar Configuration .............................................. 35

Data Output Coding .................................................................. 36

Excitation Currents .................................................................... 36

ADC Power-On .......................................................................... 36

Typical Performance Characteristics ........................................... 37

Functional Description .................................................................. 39

Interrupt Vectors ........................................................................ 86

Hardware Design Considerations ................................................ 87

External Memory Interface ....................................................... 87

Power Supplies ............................................................................ 87

Rev. A | Page 2 of 108

ADuC845/ADuC847/ADuC848

Power-On Reset Operation........................................................88

Power Consumption ...................................................................88

Power-Saving Modes ..................................................................88

Grounding and Board Layout Recommendations .................89

Other Hardware Considerations...............................................90

QuickStart Development System ..................................................94

QuickStart-PLUS Development System ..................................94

Timing Specifications .....................................................................95

Outline Dimensions......................................................................104

Ordering Guide .........................................................................105

REVISION HISTORY

6/04—Changed from Rev. 0 to Rev. A

Changes to Figure 5.........................................................................17

Changes to Figure 6.........................................................................18

Changes to Figure 7.........................................................................19

Changes to Table 5 ..........................................................................24

Changes to Table 24 ........................................................................41

Changes to Table 25 ........................................................................43

Changes to Table 26 ........................................................................44

Changes to Table 27 ........................................................................45

Changes to User Download Mode Section ..................................50

Added Figure 51 and Renumbered Subsequent Figures ............50

Edits to the DACH/DACL Data Registers Section .....................53

Changes to Table 34 ........................................................................56

Added SPIDAT: SPI Data Register Section..................................65

Changes to Table 42 ........................................................................67

Changes to Table 43 ........................................................................68

Changes to Table 44 ........................................................................69

Changes to Table 45 ........................................................................71

Changes to Table 50 ........................................................................75

Changes to Timer/Counter 0 and 1 Data Registers Section......76

Changes to Table 54 ........................................................................80

Added the SBUF—UART Serial Port Data Register Section.....80

Addition to the Timer 3 Generated Baud Rates Section............83

Added Table 57 and Renumbered Subsequent Tables................84

Changes to Table 61 ........................................................................86

4/04—Revision 0: Initial Version

Rev. A | Page 3 of 108

ADuC845/ADuC847/ADuC848

SPECIFICATIONS 1

AV DD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV DD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V, REFIN(–) = AGND; AGND =

DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz crystal; all specifications T MIN to T MAX , unless otherwise noted. Input buffer on for primary

ADC, unless otherwise noted. Core speed = 1.57 MHz (default CD = 3), unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit

Conditions

PRIMARY ADC

Conversion Rate

5.4

105

Chop on (ADCMODE.3 = 0)

16.06

1365

Chop off (ADCMODE.3 = 1)

No Missing Codes 2

Bits

≤26.7 Hz update rate with chop enabled

Bits

≤80.3 Hz update rate with chop disabled

Resolution (ADuC845/ADuC847)

See Table 11 and Table 15

Resolution (ADuC848)

See Table 13 and Table 17

Output Noise (ADuC845/ADuC847) See Table 10 and Table 14

µV (rms)

Output noise varies with selected update rates,

gain range, and chop status.

Output Noise (ADuC848)

See Table 12 and Table 16

µV (rms)

Output noise varies with selected update rates,

gain range and chop status.

Integral Nonlinearity

±15

ppm of FSR 1 LSB 16

Offset Error 3

±3

µV

Chop on

Chop off, offset error is in the order of the noise

for the programmed gain and update rate

following a calibration.

Offset Error Drift vs. Temperature 2

±10

nV/°C

Chop on (ADCMODE.3 = 0)

±200

nV/°C

Chop off (ADCMODE.3 = 1)

Full-Scale Error 4

ADuC845/ADuC847

±10

µV

±20 mV to ±2.56 V

ADuC848

±10

µV

±20 mV to ±640 mV

±0.5

LSB 16

±1.28 V to ±2.56 V

Gain Error Drift vs. Temperature 4

±0.5

ppm/°C

Power Supply Rejection

AIN = 1 V, ±2.56 V, chop enabled

113

AIN = 7.8 mV, ±20 mV, chop enabled

AIN = 1 V, ±2.56 V, chop disabled 2

PRIMARY ADC ANALOG INPUTS

Differential Input Voltage Ranges 5, 6

Gain = 1 to 128

Bipolar Mode (ADC0CON1.5 = 0)

±1.024 ×

V REF /GAIN

V REF = REFIN(+) − REFIN(−) or

REFIN2(+) − REFIN2(−) (or Int 1.25 V REF )

Unipolar Mode (ADC0CON1.5 = 1)

0 – 1.024 ×

V REF /GAIN

V REF = REFIN(+) − REFIN(−) or

REFIN2(+) − REFIN2(−) (or Int 1.25 V REF )

ADC Range Matching

±2

µV

AIN = 18 mV, chop enabled

Common-Mode Rejection DC

Chop enabled, chop disabled

On AIN

AIN = 7.8 mV, range = ±20 mV

113

AIN = 1 V, range = ±2.56 V

Common-Mode Rejection

50 Hz/60 Hz 2

50 Hz/60 Hz ± 1 Hz, 16.6 Hz and 50 Hz update

rate, chop enabled, REJ60 enabled

On AIN

AIN = 7.8 mV, range = ±20 mV

AIN = 1 V, range = ±2.56 V

Footnotes at end of table.

Rev. A | Page 4 of 108

ADuC845/ADuC847/ADuC848

Parameter

Min

Typ

Max

Unit

Conditions

Normal Mode Rejection 50 Hz/60 Hz 2

On AIN

50 Hz/60 Hz ± 1 Hz, 16.6 Hz Fadc, SF = 52H,

chop on, REJ60 on

100

50 Hz ± 1 Hz, 16.6 Hz Fadc, SF = 52H, chop on

50 Hz/60 Hz ± 1 Hz, 50 Hz Fadc, SF = 52H,

chop off, REJ60 on

100

50 Hz ± 1 Hz, 50 Hz Fadc, SF = 52H, chop off

Analog Input Current 2

±1

T MAX = 85°C, buffer on

±5

T MAX = 125°C, buffer on

Analog Input Current Drift

±5

pA/°C

T MAX = 85°C, buffer on

±15

pA/°C

T MAX = 125°C, buffer on

Average Input Current

±125

nA/V

±2.56 V range, buffer bypassed

Average Input Current Drift

±2

pA/V/°C

Buffer bypassed

Absolute AIN Voltage Limits 2

A GND +

0.1

AV DD −

0.1

AIN1…AIN10 and AINCOM with buffer enabled

Absolute AIN Voltage Limits 2

A GND −

0.03

AV DD +

0.03

AIN1…AIN10 and AINCOM with buffer bypassed

EXTERNAL REFERENCE INPUTS

REFIN(+) to REFIN(–) Voltage

2.5

REFIN refers to both REFIN and REFIN2

REFIN(+) to REFIN(–) Range 2

AV DD

REFIN refers to both REFIN and REFIN2

Average Reference Input Current

±1

µA/V

Both ADCs enabled

Average Reference Input Current

Drift

±0.1

nA/V/°C

NOXREF Trigger Voltage

0.3

0.65

NOXREF (ADCSTAT.4) bit active if V REF > 0.3 V, and

inactive if V REF > 0.65 V

Common-Mode Rejection

DC Rejection

125

AIN = 1 V, range = ±2.56 V

50 Hz/60 Hz Rejection 2

50 Hz/60 Hz ± 1 Hz, AIN = 1 V,

range = ±2.56 V, SF = 82

Normal Mode Rejection 50 Hz/60 Hz 2

50 Hz/60 Hz ±1 Hz, AIN = 1 V, range = ±2.56 V,

SF = 52H, chop on, REJ60 on

100

50 Hz ± 1 Hz, AIN = 1 V, range = ±2.56 V,

SF = 52H, chop on

50 Hz/60 Hz ± 1 Hz, AIN = 1 V, range = ±2.56 V,

SF = 52H, chop off, REJ60 on

100

50 Hz ± 1 Hz, AIN = 1 V, range = ±2.56 V,

SF = 52H, chop off

AUXILIARY ADC (ADuC845 Only)

Conversion Rate

5.4

105

Chop on

16.06

1365

Chop off

No Missing Codes 2

Bits

≤26.7 Hz update rate, chop enabled

Bits

80.3 Hz update rate, chop disabled

Resolution

See Table 19 and Table 21

Output Noise

See Table 18 and Table 20

Output noise varies with selected update rates.

Integral Nonlinearity

±15

ppm of FSR 1 LSB 16

Offset Error 3

±3

µV

Chop on

±0.25

LSB 16

Chop off

Offset Error Drift 2

nV/°C

Chop on

200

nV/°C

Chop off

Full-Scale Error 4

±0.5

LSB 16

Gain Error Drift 4

±0.5

ppm/°C

Power Supply Rejection

AIN = 1 V, range = ±2.56 V, chop enabled

AIN = 1 V, range = ±2.56 V, chop disabled

Footnotes at end of table.

Rev. A | Page 5 of 108

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