74HC_HCT173_CNV_2.pdf

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Quad D-type flip-flop; positive-edge trigger; 3-state
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
·
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
·
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
·
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT173
Quad D-type flip-flop; positive-edge
trigger; 3-state
Product specification
File under Integrated Circuits, IC06
December 1990
21701051.007.png
Philips Semiconductors
Product specification
Quad D-type flip-flop; positive-edge trigger; 3-state
74HC/HCT173
FEATURES
synchronously with the LOW- to -HIGH clock (CP)
transition. When one or both E n inputs are HIGH one
set-up time prior to the LOW-to-HIGH clock transition, the
register will retain the previous data. Data inputs and clock
enable inputs are fully edge-triggered and must be stable
only one set-up time prior to the LOW-to-HIGH clock
transition.
·
Gated input enable for hold (do nothing) mode
·
Gated output enable control
·
Edge-triggered D-type register
·
Asynchronous master reset
·
Output capability: bus driver
The master reset input (MR) is an active HIGH
asynchronous input. When MR is HIGH, all four flip-flops
are reset (cleared) independently of any other input
condition.
·
I CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT173 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT173 are 4-bit parallel load registers with
clock enable control, 3-state buffered outputs (Q 0 to Q 3 )
and master reset (MR).
The 3-state output buffers are controlle d by a 2-in put NOR
gate. When both output enable inputs (OE 1 and OE 2 ) are
LOW, the data in the regist er is presented to the Q n
outputs. When one or both OE n inputs are HIGH, the
outputs are forced to a high impedance OFF-state. The
3-state output buffers are completely independent of the
register operation; the OE n transition does not affect the
clock and reset operations.
When the two data enable inputs (E 1 and E 2 ) are LOW, the
data on the D n inputs is loaded into the register
QUICK REFERENCE DATA
GND = 0 V; T amb =25 ° C; t r =t f =6ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
HCT
t PHL / t PLH
propagation delay
CP to Q n
MR to Q n
C L = 15 pF; V CC =5V
17
13
17
17
ns
ns
f max
maximum clock frequency
88
88
MHz
C I
input capacitance
3.5
3.5
pF
C PD
power dissipation
capacitance per flip-flop
notes 1 and 2
20
20
pF
Notes
1. C PD is used to determine the dynamic power dissipation (P D in
m
W):
P D =C PD ´
V CC 2
´
f i +å
(C L ´
V CC 2
´
f o ) where:
f i = input frequency in MHz
f o = output frequency in MHz
å
f o ) = sum of outputs
C L = output load capacitance in pF
V CC = supply voltage in V
2. For HC the condition is V I = GND to V CC
For HCT the condition is V I = GND to V CC -
(C L ´
V CC 2
´
1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information” .
December 1990
2
21701051.008.png
Philips Semiconductors
Product specification
Quad D-type flip-flop; positive-edge trigger; 3-state
74HC/HCT173
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1, 2
OE 1 , OE 2
output enable input (active LOW)
3, 4, 5, 6
Q 0 to Q 3
3-state flip-flop outputs
7
CP
clock input (LOW-to-HIGH, edge-triggered)
8
G N D
ground (0 V)
9, 10
E 1 , E 2
data enable inputs (active LOW)
14, 13, 12, 11
D 0 to D 3
data inputs
15
MR
asynchronous master reset (active HIGH)
16
V CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
21701051.009.png 21701051.010.png 21701051.001.png 21701051.002.png
Philips Semiconductors
Product specification
Quad D-type flip-flop; positive-edge trigger; 3-state
74HC/HCT173
Fig.4 Functional diagram.
FUNCTION TABLE
INPUTS
OUTPUTS
REGISTER OPERATING MODES
MR CP E 1 E 2 D n
Q n (register)
reset (clear)
H
X
X X
X
L
parallel load
L
L
­
­
l
l
l
l
l
h
L
H
hold (no change)
L
L
X
X
h
X
X
h
X
X
q n
q n
3-STATE BUFFER OPERATING MODES
INPUTS OUTPUTS
Q n (register) OE 1 OE 2 Q 0 Q 1 Q 2 Q 3
read
L
H
L
L
L
L
L
H
L
H
L
H
L
H
disabled
X
X
H
X
X
H
Z
Z
Z
Z
Z
Z
Z
Z
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced input (or output)
one set-up time prior to the LOW-to-HIGH CP transition
X = don’t care
Z = high impedance OFF-state
­ = LOW-to-HIGH CP transition
December 1990
4
21701051.003.png 21701051.004.png 21701051.005.png
Philips Semiconductors
Product specification
Quad D-type flip-flop; positive-edge trigger; 3-state
74HC/HCT173
Fig.5 Logic diagram.
December 1990
5
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