74HC_HCT251_CNV_2.pdf
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8-input multiplexer; 3-state
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
·
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
·
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
·
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT251
8-input multiplexer; 3-state
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
8-input multiplexer; 3-state
74HC/HCT251
FEATURES
The 74HC/HCT251 are the logic implementations of
single-pole 8-position switches with the state of three
select inputs (S
0
,S
1
,S
2
) co
nt
rolling the switch positions.
Assertion (Y) and negatio
n (
Y) outputs are both provided.
The output enable input (OE) is active LOW. The logic
function provided at the output, when activated, is:
·
True and complement outputs
·
Both outputs are 3-state for further multiplexer
expansion
·
Multifunction capability
·
Permits multiplexing from n-lines to one line
Y=OE.(
I
0
.S
0
.
S
1
.S
2
+
I
1
.S
0
.
S
1
.S
2
+
·
Output capability: standard
I
3
.S
0
.
S
1
.S
2
+
+
I
4
.
S
0
.S
1
.S
2
+
I
5
.S
0
.S
1
.S
2
+
+
I
2
.
S
0
.
S
1
.S
2
+
·
I
CC
category: MSI
I
7
.S
0
.S
1
.S
2
)
Both outputs are in the high impedance OFF-state (Z)
when the output enable input is HIGH, allowing multiplexer
expansion by tying the outputs.
I
6
.S
0
.S
1
.S
2
+
GENERAL DESCRIPTION
The 74HC/HCT251 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
C
L
= 15 pF; V
CC
= 5 V
I
n
to
Y
15
19
ns
I
n
to Y
17
19
ns
S
n
to
Y
20
20
ns
S
n
to Y
21
21
ns
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per package
notes 1 and 2
44
46
pF
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
m
W):
P
D
= C
PD
´
V
CC
2
´
f
i
+å
(C
L
´
V
CC
2
´
f
o
) where:
´
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
f
i
= input frequency in MHz
f
o
= output frequency in MHz
å
(C
L
´
V
CC
2
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
December 1990
2
+
Philips Semiconductors
Product specification
8-input multiplexer; 3-state
74HC/HCT251
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
4, 3, 2, 1, 15, 14, 13, 12
I
0
to I
7
multiplexer inputs
5
Y
multiplexer output
6
Y
complementary multiplexer output
7
OE
3-state output enable input (active LOW)
8
GND
ground (0 V)
11, 10, 9
S
0
,S
1
,S
2
select inputs
16
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-input multiplexer; 3-state
74HC/HCT251
FUNCTION TABLE
INPUTS
OUTPUTS
OE
S
2
S
1
S
0
I
0
I
1
I
2
I
3
I
4
I
5
I
6
I
7
Y
Y
H
X
X
X
X
X
X
X
X
X
X
X
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
X
X
X
X
X
X
X
X
L
H
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
L
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
L
H
X
X
X
X
X
X
X
X
H
L
H
L
L
H
L
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
L
H
H
L
H
L
L
H
L
H
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
8-input multiplexer; 3-state
74HC/HCT251
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(
°
C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
V
CC
(V)
+
25
-
40 to
+
85
-
40 to
+
125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
I
n
to Y
50
18
14
170
34
29
215
43
37
255
51
43
ns
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propa
ga
tion delay
I
n
to Y
55
20
16
175
35
30
220
44
37
265
53
45
ns
2.0
4.5
6.0
Fig.7
t
PHL
/ t
PLH
propagation delay
S
n
to Y
66
24
19
205
41
35
255
51
43
310
62
53
ns
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propag
a
tion delay
S
n
to Y
69
25
20
205
41
35
255
51
43
310
62
53
ns
2.0
4.5
6.0
Fig.7
t
PZH
/ t
PZL
3
-sta
te ou
tp
ut enable time
OE to Y, Y
36
13
10
140
28
24
175
35
30
210
42
36
ns
2.0
4.5
6.0
Fig.7
t
PHZ
/ t
PLZ
3
-sta
te ou
tp
ut disable time
OE to Y, Y
39
14
11
140
28
24
170
35
30
210
42
36
ns
2.0
4.5
6.0
Fig.7
t
THL
/ t
TLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Figs 6 and 7
December 1990
5
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