74HC_T00.pdf

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT00

Quad 2-input NAND gate

Product speciﬁcation

File under Integrated Circuits, IC06

December 1990

Philips Semiconductors

Product speciﬁcation

Quad 2-input NAND gate

74HC/HCT00

FEATURES

Output capability: standard

I CC category: SSI

GENERAL DESCRIPTION

The 74HC/HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).

They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT00 provide the 2-input NAND function.

QUICK REFERENCE DATA

GND = 0 V; T amb = 25

C; t r = t f = 6 ns

TYPICAL

SYMBOL

PARAMETER

CONDITIONS

UNIT

HCT

t PHL / t PLH

propagation delay nA, nB to nY

C L = 15 pF; V CC =5V 7

C I

input capacitance

3.5

C PD

power dissipation capacitance per gate notes 1 and 2

Notes

1. C PD is used to determine the dynamic power dissipation (P D in

W):

P D = C PD ´

V CC 2

f i +

(C L ´

V CC 2

f o ) where:

f o ) = sum of outputs

2. For HC the condition is V I = GND to V CC

For HCT the condition is V I = GND to V CC -

f i = input frequency in MHz

f o = output frequency in MHz

C L = output load capacitance in pF

V CC = supply voltage in V

(C L ´

V CC 2

1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information” .

December 1990

Philips Semiconductors

Product speciﬁcation

Quad 2-input NAND gate

74HC/HCT00

PIN DESCRIPTION

PIN NO.

SYMBOL

NAME AND FUNCTION

1, 4, 9, 12

1A to 4A

data inputs

2, 5, 10, 13

1B to 4B

data inputs

3, 6, 8, 11

1Y to 4Y

data outputs

GND

ground (0 V)

V CC

positive supply voltage

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

FUNCTION TABLE

INPUTS

OUTPUT

Note

1. H = HIGH voltage level

L = LOW voltage level

Fig.4 Functional diagram.

Fig.5 Logic diagram (one gate).

December 1990

Philips Semiconductors

Product speciﬁcation

Quad 2-input NAND gate

74HC/HCT00

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications” .

Output capability: standard

I CC category: SSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t r = t f = 6 ns; C L = 50 pF

T amb (

TEST CONDITIONS

74HC

SYMBOL PARAMETER

UNIT

+25

40 to +85

40 to +125

V CC

(V)

WAVEFORMS

min. typ. max. min. max. min. max.

t PHL / t PLH

propagation delay

nA, nB to nY

115

135

2.0

4.5

6.0

Fig.6

t THL / t TLH

output transition

time

110

2.0

4.5

6.0

Fig.6

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications” .

Output capability: standard

I CC category: SSI

Note to HCT types

The value of additional quiescent supply current (

I CC ) for a unit load of 1 is given in the family specifications.

To determine

I CC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT

UNIT LOAD COEFFICIENT

nA, nB

1.50

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t r = t f = 6 ns; C L = 50 pF

T amb (

TEST CONDITIONS

74HCT

SYMBOL PARAMETER

UNIT

+25

- 40 to +85

- 40 to +125

V CC

(V)

WAVEFORMS

min. typ. max. min. max. min. max.

t PHL / t PLH propagation delay

nA, nB to nY

4.5 Fig.6

t THL / t TLH output transition time

4.5 Fig.6

December 1990

Philips Semiconductors

Product speciﬁcation

Quad 2-input NAND gate

74HC/HCT00

AC WAVEFORMS

HC : V M = 50%; V I = GND to V CC

HCT: V M = 1.3 V; V I = GND to 3 V.

Fig.6 Waveforms showing the input (nA, nB) to output (nY) propagation delays and the output transition times.

PACKAGE OUTLINES

See “74HC/HCT/HCU/HCMOS Logic Package Outlines” .

December 1990

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