ATmega169V_L.pdf

Features

• High Performance, Low Power AVR ® 8-Bit Microcontroller

• Advanced RISC Architecture

– 130 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 4 MIPS Throughput at 4 MHz

– On-Chip 2-cycle Multiplier

• Non-volatile Program and Data Memories

– 16K bytes of In-System Self-Programmable Flash

Endurance: 10,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– 512 bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

– 1K byte Internal SRAM

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– 4 x 25 Segment LCD Driver

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Four PWM Channels

– 8-channel, 10-bit ADC

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Universal Serial Interface with Start Condition Detector

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated Oscillator

– External and Internal Interrupt Sources

– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby

• I/O and Packages

– 53 Programmable I/O Lines and 1 Input Line

– 64-lead TQFP and 64-pad MLF

• Operating Voltage:

– 1.8 - 3.6V for ATmega169V

– 2.7 - 3.6V for ATmega169L

• Temperature Range:

–0

8-bit

Microcontroller

with 16K Bytes

In-System

Programmable

Flash

ATmega169V

ATmega169L

Advance

Information

C to 70

• Speed Grade:

– 0 - 1 MHz for ATmega169V

– 0 - 4 MHz for ATmega169L

• Ultra-Low Power Consumption

– Active Mode:

1 MHz, 1.8V: 300 µ A

32 kHz, 1.8V: 20 µ A (including Oscillator)

32 kHz, 1.8V: TBD (including Oscillator and LCD)

– Power-down Mode:

0.5 µ A at 1.8V

Rev. 2514C–AVR–11/02

Pin Configurations

Figure 1. Pinout ATmega169

LCDCAP

PA3 (COM3)

(RXD/PCINT0) PE0

PA4 (SEG0)

INDEX CORNER

(TXD/PCINT1) PE1

PA5 (SEG1)

(XCK/AIN0/PCINT2) PE2

PA6 (SEG2)

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

PA7 (SEG3)

PG2 (SEG4)

(DI/SDA/PCINT5) PE5

PC7 (SEG5)

(DO/PCINT6) PE6

ATmega169

PC6 (SEG6)

(CLKO/PCINT7) PE7

PC5 (SEG7)

(SS/PCINT8) PB0

PC4 (SEG8)

(SCK/PCINT9) PB1

PC3 (SEG9)

(MOSI/PCINT10) PB2

PC2 (SEG10)

(MISO/PCINT11) PB3

PC1 (SEG11)

(OC0A/PCINT12) PB4

PC0 (SEG12)

(OC1A/PCINT13) PB5

PG1 (SEG13)

(OC1B/PCINT14) PB6

PG0 (SEG14)

Disclaimer

Typical values contained in this data sheet are based on simulations and characteriza-

tion of other AVR microcontrollers manufactured on the same process technology. Min

and Max values will be available after the device is characterized.

ATmega169V/L

2514C–AVR–11/02

ATmega169V/L

Overview

The ATmega169 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing

powerful instructions in a single clock cycle, the ATmega169 achieves throughputs approaching 1 MIPS per MHz allowing

the system designer to optimize power consumption versus processing speed.

Block Diagram

Figure 2. Block Diagram

PF0 - PF7

PA0 - PA7

PC0 - PC7

VCC

GND

PORTF DRIVERS

PORTA DRIVERS

PORTC DRIVERS

DATA REGISTER

PORTF

DATA DIR.

REG. PORTF

DATA REGISTER

PORTA

DATA DIR.

REG. PORTA

DATA REGISTER

PORTC

DATA DIR.

REG. PORTC

8-BIT DATA BUS

AVCC

CALIB. OSC

AGND

ADC

INTERNAL

OSCILLATOR

AREF

OSCILLATOR

JTAG TAP

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

TIMING AND

CONTROL

ON-CHIP DEBUG

PROGRAM

FLASH

SRAM

MCU CONTROL

LCD

CONTROLLER/

DRIVER

BOUNDARY-

SCAN

INSTRUCTION

GENERAL

PURPOSE

REGISTERS

TIMER/

COUNTERS

PROGRAMMING

LOGIC

INSTRUCTION

DECODER

INTERRUPT

UNIT

CONTROL

LINES

ALU

EEPROM

AVR CPU

STATUS

USART0

UNIVERSAL

SERIAL INTERFACE

SPI

DATA REGISTER

PORTE

DATA DIR.

REG. PORTE

DATA REGISTER

PORTB

DATA DIR.

REG. PORTB

DATA REGISTER

PORTD

DATA DIR.

REG. PORTD

DATA REG.

PORTG

DATA DIR.

REG. PORTG

PORTE DRIVERS

PORTB DRIVERS

PORTD DRIVERS

PORTG DRIVERS

PE0 - PE7

PB0 - PB7

PD0 - PD7

PG0 - PG4

2514C–AVR–11/02

The AVR core combines a rich instruction set with 32 general purpose working registers.

All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing

two independent registers to be accessed in one single instruction executed in one clock

cycle. The resulting architecture is more code efficient while achieving throughputs up to

ten times faster than conventional CISC microcontrollers.

The ATmega169 provides the following features: 16K bytes of In-System Programmable

Flash with Read-While-Write capabilities, 512 bytes EEPROM, 1K byte SRAM,

53 general purpose I/O lines and one input line, 32 general purpose working registers, a

JTAG interface for Boundary-scan, On-chip Debugging support and programming, a

complete On-chip LCD controller with internal step-up voltage, three flexible

Timer/Counters with compare modes, internal and external interrupts, a serial program-

mable USART, Universal Serial Interface with Start Condition Detector, an 8-channel,

10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port,

and five software selectable power saving modes. The Idle mode stops the CPU while

allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue function-

ing. The Power-down mode saves the register contents but freezes the Oscillator,

disabling all other chip functions until the next interrupt or hardware reset. In Power-

save mode, the asynchronous timer and the LCD controller continues to run, allowing

the user to maintain a timer base and operate the LCD display while the rest of the

device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules

except asynchronous timer, LCD controller and ADC, to minimize switching noise during

ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the

rest of the device is sleeping. This allows very fast start-up combined with low-power

consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology.

The On-chip ISP Flash allows the program memory to be reprogrammed In-System

through an SPI serial interface, by a conventional non-volatile memory programmer, or

by an On-chip Boot program running on the AVR core. The Boot program can use any

interface to download the application program in the Application Flash memory. Soft-

ware in the Boot Flash section will continue to run while the Application Flash section is

updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU

with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega169 is

a powerful microcontroller that provides a highly flexible and cost effective solution to

many embedded control applications.

The ATmega169 AVR is supported with a full suite of program and system development

tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir-

cuit Emulators, and Evaluation kits.

ATmega169V/L

2514C–AVR–11/02

ATmega169V/L

Pin Descriptions

VCC

Digital supply voltage.

GND

Ground.

Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port A output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port A pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port A also serves the functions of various special features of the ATmega169 as listed

on page 57 .

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port B output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port B pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATmega169 as listed

on page 58 .

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port C output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port C pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port C also serves the functions of special features of the ATmega169 as listed on page

61 .

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port D output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port D pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega169 as listed

on page 63 .

Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port E output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port E pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port E also serves the functions of various special features of the ATmega169 as listed

on page 65 .

Port F (PF7..PF0)

Port F serves as the analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.

Port pins can provide internal pull-up resistors (selected for each bit). The Port F output

buffers have symmetrical drive characteristics with both high sink and source capability.

As inputs, Port F pins that are externally pulled low will source current if the pull-up

2514C–AVR–11/02

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