atmega162.pdf

Features

• High-performance, Low-power AVR ® 8-bit Microcontroller

Advanced RISC Architecture

– 131 Powerful Instructions – Most Single-clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

High Endurance Non-volatile Memory segments

– 16K Bytes of In-System Self-programmable Flash program memory

– 512 Bytes EEPROM

– 1K Bytes Internal SRAM

– Write/Erase cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C (1)

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Up to 64K Bytes Optional External Memory Space

– Programming Lock for Software Security

JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– Two 16-bit Timer/Counters with Separate Prescalers, Compare Modes, and

Capture Modes

– Real Time Counter with Separate Oscillator

– Six PWM Channels

– Dual Programmable Serial USARTs

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended Standby

I/O and Packages

– 35 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, and 44-pad MLF

Operating Voltages

– 1.8 - 5.5V for ATmega162V

– 2.7 - 5.5V for ATmega162

Speed Grades

– 0 - 8 MHz for ATmega162V (see Figure 113 on page 266 )

– 0 - 16 MHz for ATmega162 (see Figure 114 on page 266 )

8-bit

Microcontroller

with 16K Bytes

In-System

Programmable

Flash

ATmega162

ATmega162V

2513K–AVR–07/09

Configurations

Figure 1. Pinout ATmega162

PDIP

(OC0/T0) PB0

(OC2/T1) PB1

(RXD1/AIN0) PB2

(T XD1 /AIN1) PB3

(SS/OC3B) PB4

(MOSI) PB5

(MISO) PB6

(SC K) PB7

RESET

(RXD0) PD0

(TXD0) PD1

(INT0/XCK1) PD2

(INT1/ICP3) PD3

(TOSC1/XCK0/OC3A) PD4

(OC1A/TO SC2) PD5

( WR) PD6

(RD) PD7

XTAL2

XTAL1

GND

VCC

PA0 (AD0/PCINT0)

PA1 (AD1/PCINT1)

PA2 (AD2/PCINT2)

PA3 (AD3/PCINT3)

PA4 (AD4/PCINT4)

PA5 (AD5/PCINT5)

PA6 (AD6/PCINT6)

PA7 (AD7/PCINT7)

PE0 (ICP1/INT2)

PE1 (ALE)

PE2 (OC1B)

PC7 (A15/TDI/PCINT15)

PC6 (A14/TDO/PCINT14)

PC5 (A13/TMS/PCINT13)

PC4 (A12/TCK/PCINT12)

PC3 (A11/PCINT11)

PC2 (A10/PCINT10)

PC1 (A9/PCINT9)

PC0 (A8/PCINT8)

TQFP/MLF

(MOSI) PB5

(MISO) PB6

(SC K) PB7

RESET

(RXD0) PD0

VCC

(TXD0) PD1

(INT0/XCK1) PD2

(INT1/ICP3) PD3

(TOSC1/XCK0/OC3A) PD4

(OC1A/TOSC2) PD5

44 42 40 38 36 34

43 41 39 37 35

PA4 (AD4/PCINT4)

PA5 (AD5/PCINT5)

PA6 (AD6/PCINT6)

PA7 (AD7/PCINT7)

PE0 (ICP1/INT2)

GND

PE1 (ALE)

PE2 (OC1B)

PC7 (A15/TDI/PCINT15)

PC6 (A14/TDO/PCINT14)

PC5 (A13/TMS/PCINT13)

13 15 17 19 21

12 14 16 18 20 22

NOTE:

MLF bottom pad should

be soldered to ground.

Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of

other AVR microcontrollers manufactured on the same process technology. Min and Max values

will be available after the device is characterized.

ATmega162/V

2513K–AVR–07/09

ATmega162/V

Overview

The ATmega162 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC

architecture. By executing powerful instructions in a single clock cycle, the ATmega162

achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize

power consumption versus processing speed.

Block Diagram

Figure 2. Block Diagram

PA0 - PA7

PE0 - PE2

PC0 - PC7

VCC

PORTA DRIVERS/BUFFERS

PORTE

DRIVERS/

BUFFERS

PORTC DRIVERS/BUFFERS

GND

PORTA DIGITAL INTERFACE

PORTE

DIGITAL

INTERFACE

PORTC DIGITAL INTERFACE

PROGRAM

COUNTER

STACK

POINTER

INTERNAL

OSCILLATOR

XTA L1

PROGRAM

FLASH

SRAM

WATCHDOG

TIMER

OSCILLATOR

XTAL2

INSTRUCTION

GENERAL

PURPOSE

REGISTERS

MCU CTRL.

& TIMING

RESET

INSTRUCTION

DECODER

INTERRUPT

UNIT

INTERNAL

CALIBRATED

OSCILLATOR

CONTROL

LINES

ALU

TIMERS/

COUNTERS

OSCILLATOR

AVR CPU

STATUS

EEPROM

PROGRAMMING

LOGIC

SPI

USART0

COMP.

INTERFACE

USART1

PORTB DIGITAL INTERFACE

PORTD DIGITAL INTERFACE

PORTB DRIVERS/BUFFERS

PORTD DRIVERS/BUFFERS

PB0 - PB7

PD0 - PD7

2513K–AVR–07/09

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATmega162 provides the following features: 16K bytes of In-System Programmable Flash

with Read-While-Write capabilities, 512 bytes EEPROM, 1K bytes SRAM, an external memory

interface, 35 general purpose I/O lines, 32 general purpose working registers, a JTAG interface

for Boundary-scan, On-chip Debugging support and programming, four flexible Timer/Counters

with compare modes, internal and external interrupts, two serial programmable USARTs, a pro-

grammable Watchdog Timer with Internal Oscillator, an SPI serial port, and five software

selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,

Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode

saves the register contents but freezes the Oscillator, disabling all other chip functions until the

next interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to

run, allowing the user to maintain a timer base while the rest of the device is sleeping. In

Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping.

This allows very fast start-up combined with low-power consumption. In Extended Standby

mode, both the main Oscillator and the Asynchronous Timer continue to run.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI

serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot Pro-

gram running on the AVR core. The Boot Program can use any interface to download the

Application Program in the Application Flash memory. Software in the Boot Flash section will

continue to run while the Application Flash section is updated, providing true Read-While-Write

operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a

monolithic chip, the Atmel ATmega162 is a powerful microcontroller that provides a highly flexi-

ble and cost effective solution to many embedded control applications.

The ATmega162 AVR is supported with a full suite of program and system development tools

including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators,

and evaluation kits.

ATmega161 and

ATmega162

Compatibility

The ATmega162 is a highly complex microcontroller where the number of I/O locations super-

sedes the 64 I/O locations reserved in the AVR instruction set. To ensure back-ward

compatibility with the ATmega161, all I/O locations present in ATmega161 have the same loca-

tions in ATmega162. Some additional I/O locations are added in an Extended I/O space starting

from 0x60 to 0xFF, (i.e., in the ATmega162 internal RAM space). These locations can be

reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT

instructions. The relocation of the internal RAM space may still be a problem for ATmega161

users. Also, the increased number of Interrupt Vectors might be a problem if the code uses

absolute addresses. To solve these problems, an ATmega161 compatibility mode can be

selected by programming the fuse M161C. In this mode, none of the functions in the Extended

I/O space are in use, so the internal RAM is located as in ATmega161. Also, the Extended Inter-

rupt Vec-tors are removed. The ATmega162 is 100% pin compatible with ATmega161, and can

replace the ATmega161 on current Printed Circuit Boards. However, the location of Fuse bits

and the electrical characteristics differs between the two devices.

ATmega161

Compatibility Mode

Programming the M161C will change the following functionality:

The extended I/O map will be configured as internal RAM once the M161C Fuse is

programmed.

ATmega162/V

2513K–AVR–07/09

ATmega162/V

The timed sequence for changing the Watchdog Time-out period is disabled. See “Timed

Sequences for Changing the Configuration of the Watchdog Timer” on page 56 for details.

The double buffering of the USART Receive Registers is disabled. See “AVR USART vs.

AVR UART – Compatibility” on page 168 for details.

Pin change interrupts are not supported (Control Registers are located in Extended I/O).

One 16 bits Timer/Counter (Timer/Counter1) only. Timer/Counter3 is not accessible.

Note that the shared UBRRHI Register in ATmega161 is split into two separate registers in

ATmega162, UBRR0H and UBRR1H. The location of these registers will not be affected by the

ATmega161 compatibility fuse.

Pin Descriptions

VCC

Digital supply voltage

GND

Ground

Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source

capability. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will

source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

Port A also serves the functions of various special features of the ATmega162 as listed on page

72 .

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the ATmega162 as listed on page

72 .

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins

PC7(TDI), PC5(TMS) and PC4(TCK) will be activated even if a Reset occurs.

Port C also serves the functions of the JTAG interface and other special features of the

ATmega162 as listed on page 75 .

2513K–AVR–07/09

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