HP G60 COMPAQ CQ60 - WISTRON HBU16 1.2 - REV 1.pdf - Compaq-HP - marco.marc

HBU16-1.2 Intel UMA Block Diagram

SYSTEM DC/DC

TPS51125

INPUTS

OUTPUTS

Project code : 91.4FQ01.001

PCB P/N : 09233

Revision : 1

+5VALW

Intel CPU

DCBATOUT

+3VALW

Clock Generator

ICS9LPRS355

+3VL

Penryn SV

SYSTEM DC/DC

TPS51116

APL5912

3,4,5

INPUTS

OUTPUTS

INPUTS

+1.8V

OUTPUTS

+1.5VS

FSB

800/1066MHz

+0.9VS

DCBATOUT

+1.8V

CRT

RGB CRT

SYSTEM DC/DC

DDRII

667/800

1600X1200@75

Slot 0

Cantiga-GM/GL

AGTL+ CPU I/F

INTEGRATED GRAHPICS

DDRII 667/800 Channel A

RT8209

LCD

DDR I/F

LVDS(Dual Channel)

INPUTS

+5VALW

OUTPUTS

+1.05V

WXGA+

DDRII

667/800

Slot 1

DDR II 667/800 Channel B

LVDS, CRT I/F

HDMI

PCIE

6,7,8,9,10,11

MAXIM CHARGER

MAX8731

DMIx4

C-LINK

INPUTS

OUTPUTS

BT+

WEBCAM

DCBATOUT

18V 3.0A

5V 100mA

INTEL

SD/MMC

MS/MS Pro/xD

Realtek

RTS5159

BLUETOOT 22

USB 2.0

CPU DC/DC

ICH9-M

ISL6269CCRZ

USB x 3

USB 2.0

Realtek

RTL8103T

INPUTS

OUTPUTS

RJ45

CONN

12 USB 2.0/1.1 ports

(10/100/1000Mb)

PCIE

+VCC_CORE

ETHERNET

10/100

SATA

HDD

High Definition Audio

DCBATOUT

0.844~1.3V

22A

4 SATA ports

AMOM

MODEM

35,36

6 PCIE ports

ODD

RJ11

CONN

ACPI 1.1

LPC I/F

PCB LAYER

CX20548-11Z

HD AUDIO

LPC Bus

PCI/PCI BRIDGE

L1:

Signal 1

HD AUDIO

CODEC

17,18,19,20,21

L2:

GND

LINE OUT

CX20583-11Z

KBC

L3:

Signal 2

WINBOND

WPCE773L

SPI

L4:

Signal 3

MIC IN

L5:

VCC

Signal 4

INTERNAL MIC

L6:

Thermal

& Fan

Mini-Card

Flash ROM

64KB

Flash ROM

Touch

PAD 30

Int.

802.11a/b/g/n

2MB

GMT G7921

2CH SPEAKER

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Block Diagram

Size

Document Number

Rev

HBU16 1.2

Date:

Monday, July 06, 2009

Sheet

ICH9M Functional Strap Definitions

ICH9 Integrated pull-up

and pull-down Resistors

Cantiga chipset and ICH9M I/O controller

Hub strapping configuration

ICH9 EDS 642879 Rev.1.5 page 92

Signal

Usage/When Sampled

Comment

ICH9 EDS 642879 Rev.1.5

Montevina Platform Design guide 22339 0.5

page 218

HDA_SDOUT

XOR Chain Entrance/

PCIE Port Config1 bit1,

Rising Edge of PWROK.

Allows entrance to XOR Chain testing when TP3

pulled low. When TP3 not pulled low at rising edge

of PWROK, sets bit1 of RPC.PC (Cofig Registers:

offset 224h). This signal has weak internal

pull-down.

SIGNAL

Resistor Type/Value

Pin Name

Strap Description

Configuration

CL_CLK[1:0]

CL_DATA[1:0]

CL_RST0#

DPRSLPVR/GPIO16

ENERGY_DETECT

PULL-UP 20K

CFG[2:0]

FSB Frequency Select 000 = FSB1067

011 = FSB667

010 = FSB800

others = Reserved

PULL-UP 20K

HDA_SYNC

PCIE config1 bit0,

Rising Edge of PWROK.

This signal has a weak internal pull-down.

Sets bit0 of PRC.PC (Config Registers: Offset

224h).

CFG[4:3]

CFG[15:14]

CFG[18:17]

Reserved

PULL-DOWN 20K

CFG8

PULL-UP 20K

GNT2#/

GPIO53

PCIE config2 bit2,

Rising Edge of PWROK.

This signal has a weak internal pull-up.

Sets bit2 of PRC.PC2 (Config Registers: Offset

224h).

HDA_BIT_CLK

PULL-DOWN 20K

CFG5

DMI x2 Select

0 = DMI x2

1 = DMI x4 (Default)

HDA_DOCK_EN#/GPIO33

PULL-UP 20K

CFG6

iTPM Host Interface

0 = The iTPM Host Interface is enabled (Note 2)

HDA_RST#

HDA_SDIN[3:0]

HDA_SDOUT

HDA_SYNC

PULL-DOWN 20K

1 = The iTPM Host Interface is disabled (default)

GPIO20

Reserved.

This signal should not be pulled high.

CFG7

Intel Management

engine crypto strap

0 = Transport Layer Security (TLS) cipher

GNT1#/

GPIO51

ESI Strap (Server Only)

Rising Edge of PWROK.

ESI compatible mode is for server platforms only.

This signal should not be pulled low for desktop

and mobile.

suite with no confidentiality

1 = TLS cipher suite with confidentiality(Default)

CFG9

PCIE Graphics Lane

0 = Reserved Lanes, 15->0, 14->1 ect..

1 = Normal operation (Default): Lane Numbered in

Order

GNT3#/

GPIO55

Top-Block Swap

override. Rising Edge

of PWROK.

Sampled low: Top-Block Swap mode (inverts A16 for

all cycles targeting FWH BIOS space).

Note: Software will not be able to clear the

Top-Swap bit until the system is rebooted

without GNT3# being pulled down.

GLAN_DOCK#

The pull-up or pull-down

active when configured

for native GLAN_DOCK#

functionality and determined

by LAN controller.

CFG10

PCIE Loopback enable 0 = Enable (Note 3)

1 = Disable (Default)

CFG[13:12] XOR/ALL

00 = Reserve

10 = XOR mode Enabled

01 = ALLZ mode Enable (Note 3)

11 = Disabled (Default)

GNT0#:

SPI_CS1#/

GPIO58

Boot BIOS Destination

Selection 0:1.

Rising Edge of PWROK.

Controllable via Boot BIOS Destination bit

(Config Registers: Offset 3410h:bit 11:10).

GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC

GNT[3:0]#/GPIO[55,53,51]

GPIO20

PULL-UP 20K

PULL-DOWN 20K

CFG16

FSB Dynamic ODT

0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled (Default)

GPIO49

PULL-UP 20K

SPI_MOSI

Integrated TPM Enable,

Rising Edge of CLPWROK.

Sample low: the Integrated TPM will be disable.

Sample high: the MCH TPM enable strap is sampled

low and the TPM Disable bit is clear, the

Integrated TPM will be enable.

CFG19

DMI Lane Reversal

0 = Normal operation (Default): Lane Numbered in

Order

1 = Reverse Lanes

DMI x4 mode [MCH->ICH]: (3->0, 2->1, 1->2 and 0->3)

DMI x2 mode [MCH->ICH]: (3->0, 2->1)

LDA[3:0]#/FHW[3:0]#

LAN_RXD[2:0]

LDRQ[0]

PULL-UP 20K

PULL-UP 15K

PULL-UP 20K

PULL-DOWN 20K

PULL-UP 20K

GPIO49

DMI Termination

Voltage. Rising Edge

of CLPWROK.

The signal is required to be low for desktop

applications and required to be high for mobile

applications.

CFG20

Digital Display Port

(SDVO/DP/iHDMI)

Concurrent with PCIe

0 = Only Digital Display Port or PCIE is

operational (Default)

1 = Digital display Port and PCIe are operating

simulataneously via the PEG port

LDRQ[1]/GPIO23

PME#

PWRBTN#

SATALED#

PCI Express Lane

Reversal. Rising Edge

of PWROK.

Signal has weak internal pull-up. Sets bit 27

of MPC.LR (Device 28: Function 0:Offset D8).

SDVO

_CTRLDATA

SDVO Present

0 = No SDVO Card Present (Default)

1 = SDVO Card Present

L_DDC_DATA Local Flat Panel (LFP)

Present

0 = LFP Disabled (Default)

1 = LFP Card Present; PCIE disabled

SPI_CS1#/GPIO58/CLGPIO6

No Reboot.

Rising Edge of PWROK.

If sampled high, the system is strapped to the

"No Reboot" mode (ICH9 will disable the TCO Timer

system reboot feature). The status is readable

via the NO REBOOT bit.

SPKR

SPI_MOSI

SPI_MISO

NOTE:

1. All strap signals are sampled with respect to the leading edge of the (G)MCH

Power OK (PWROK) signal.

2. iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of

the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6.

Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time.

SPKR

PULL-DOWN 20K

XOR Chain Entrance.

Rising Edge of PWROK.

This signal should not be pull low unless using

XOR Chain testing.

TP3

TACH_[3:0]

PULL-UP 20K

GPIO33/

HDA_DOCK

_EN#

Flash Descriptor

Security Override

Strap. Rising Edge of

PWROK.

Sampled low: the Flash Descriptor Security will be

overridden. If high, the security measures will be

in effect. This should only be enabled in

manufacturing environments using an external

pull-up resister.

TP[3]

USB[11:0][P,N]

PULL-DOWN 15K

SMBus

PCIE Routing

USB Table

page 19

USB

Thermal

Pair

Device

KBC

LANE1

LANE2

LAN

MiniCard WLAN

USB3

FREE

External USB3

BATTERY

FREE

External USB2

FREE

MINI

WLAN

ICH9M

BLUETOOTH

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

CARD_READER

FREE

CAMERA

FREE

Title

Table of Content

Clock

Generator

Size

Document Number

Rev

HBU16 1.2

Date:

Tuesday, June 30, 2009

Sheet

H_A#[35..3]

Reserve for ITP, when

install ITP connector,

install R69.

U54A

1 OF 4

H_A#3

H_A#4

H_A#5

H_A#6

H_A#7

H_A#8

H_A#9

H_A#10

H_A#11

H_A#12

H_A#13

H_A#14

H_A#15

H_A#16

H_ADS#

A3#

ADS#

H_BNR#

A4#

BNR#

A5#

BPRI#

H_BPRI#

A6#

H_DEFER#

A7#

DEFER#

+1.05VS

F21

H_DRDY#

A8#

DRDY#

H_DBSY#

A9#

DBSY#

A10#

H_BREQ#0

A11#

BR0#

56R2J-4-GP

R69

51R2F-2-GP

R69

51R2F-2-GP

A12#

D20

CPU_IERR#

R32

A13#

IERR#

+1.05VS

H_INIT#

A14#

INIT#

A15#

H_LOCK#

A16#

LOCK#

H_CPURST#

H_ADSTB#0

ADSTB0#

H_CPURST#

H_RS#[2..0]

H_REQ#[4..0]

RESET#

H_REQ#0

H_REQ#1

H_REQ#2

H_REQ#3

H_REQ#4

H_RS#0

H_RS#2

REQ0#

RS0#

H_RS#1

REQ1#

RS1#

REQ2#

RS2#

H_TRDY#

REQ3#

TRDY#

REQ4#

H_HIT#

HIT#

H_A#17

H_A#19

A17#

HITM#

H_HITM#

H_A#18

H_A#20

H_A#21

H_A#22

A18#

XDP_BPM#0

XDP_BPM#1

XDP_BPM#2

XDP_BPM#3

XDP_BPM#4

AD4

A19#

BPM0#

AD3

A20#

BPM1#

AD1

A21#

BPM2#

AC4

A22#

BPM3#

H_A#23

H_A#24

H_A#25

H_A#26

H_A#27

H_A#28

H_A#29

H_A#30

H_A#31

AC2

A23#

PRDY#

AC1

XDP_BPM#5

A24#

PREQ#

AC5

XDP_TCK

XDP_TDI

XDP_TMS

XDP_TRST#

H_THERMDA, H_THERMDC routing together,

Trace width / Spacing = 10 / 10 mil

A25#

TCK

AA6

A26#

TDI

XDP_TDO

AB3

A27#

TDO

AB5

A28#

TMS

AB6

A29#

TRST#

XDP_DBRESET#_R

C20

A30#

DBR#

A31#

H_A#32

CPU_PROCHOT#_R

A32#

H_A#33

AA4

THERMAL

A33#

H_A#34

AB2

+1.05VS

A34#

H_A#35

R31

68R2-GP

AA3

D21

A35#

PROCHOT#

A24

H_ADSTB#1

ADSTB1#

THRMDA

H_THERMDA

B25

THRMDC

H_THERMDC

H_A20M#

A20M#

H_FERR#

PM_THRMTRIP-A#

7,18

FERR#

THERMTRIP#

H_IGNNE#

IGNNE#

H_STPCLK#

STPCLK#

HCLK

A22

H_INTR

CLK_CPU_BCLK

LINT0

BCLK0

A21

H_NMI

CLK_CPU_BCLK#

LINT1

BCLK1

ITP Connector

H_SMI#

SMI#

PM_THRMTRIP#

+1.05VS

TPAD14-GP

TP4

RSVD_CPU_1

should connect to

RSVD#M4

TPAD14-GP

TP6

RSVD_CPU_2

RSVD_CPU_3

ICH9 and MCH

RSVD#N5

TPAD14-GP

TP8

without T-ing

RSVD#T2

TPAD14-GP

TP7

RSVD_CPU_4

( No stub)

RSVD#V3

TPAD14-GP

TP9

RSVD_CPU_5

RSVD_CPU_6

RSVD_CPU_7

C472

SCD47U16V2ZY-GP

R293

RSVD#B2

TEST7

TPAD14-GP

TP10

RSVD#C3

TPAD14-GP

TP15

RSVD#D2

TPAD14-GP

TP1

RSVD_CPU_8

D22

ITP1

RSVD#D22

TPAD14-GP

TP14

RSVD_CPU_9

RSVD_CPU_10

RSVD#D3

TPAD14-GP

TP5

RSVD#F6

+1.05VS

RSVD_CPU_11

TPAD14-GP

TP13

+1.05VS

KEY_NC

ITP_VDD

R277

BGA479-SKT6-GPU7

XDP_DBRESET#_R

0R2J-2-GP

XDP_DBRESET#

XDP_BPM#0

1st: 62.10079.001

2nd: 62.10053.401

XDP_BPM#1

R284

0R2J-2-GP

MCH_CLKSEL2

7,16

XDP_BPM#2

R283

0R2J-2-GP

MCH_CLKSEL1

7,16

XDP_BPM#3

R282

0R2J-2-GP

MCH_CLKSEL0

7,16

XDP_BPM#4

H_CPURST#

H_RESET#_R

XDP_BPM#5

R292

1KR2J-1-GP

XDP_TCK

+3VS

CLK_CPU_XDP#

CLK_CPU_XDP

XDP_TDO_R

R281

0R2J-2-GP

XDP_TDO

XDP_TCK

R287

XDP_TMS

XDP_TRST#

XDP_DBRESET#_R

XDP_TDI

1KR2J-1-GP

MLX-CONN28A-4-GP

+1.05VS

XDP_TDI

R66

54D9R2F-L1-GP

XDP_TMS

R63

54D9R2F-L1-GP

XDP_TDO

XDP_BPM#5

R65

54D9R2F-L1-GP

R64

54D9R2F-L1-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

XDP_TRST#

XDP_TCK

R71

54D9R2F-L1-GP

R72

54D9R2F-L1-GP

Title

CPU (1 of 2)

Size

Document Number

Rev

HBU16 1.2

Date:

Thursday, July 09, 2009

Sheet

H_DINV#[3..0]

H_DSTBN#[3..0]

H_DSTBP#[3..0]

H_DSTBN#[3..0]

H_DSTBP#[3..0]

H_D#[63..0]

U54B

2 OF 4

H_D#0

H_D#1

H_D#2

H_D#3

H_D#4

H_D#5

H_D#6

H_D#7

H_D#8

H_D#9

H_D#10

H_D#11

H_D#12

H_D#13

H_D#14

H_D#15

H_D#32

H_D#33

H_D#34

H_D#35

H_D#36

H_D#37

H_D#38

H_D#39

H_D#41

E22

Y22

D0#

D32#

F24

AB24

D1#

D33#

E26

V24

D2#

D34#

G22

V26

D3#

D35#

F23

V23

D4#

D36#

G25

T22

D5#

D37#

E25

U25

D6#

D38#

E23

U23

D7#

D39#

H_D#40

H_D#42

H_D#43

H_D#44

H_D#45

H_D#46

H_D#47

K24

Y25

D8#

D40#

G24

W22

D9#

D41#

J24

Y23

D10#

D42#

J23

W24

D11#

D43#

H22

W25

D12#

D44#

F26

AA23

D13#

D45#

K22

AA24

D14#

D46#

H23

AB25

D15#

D47#

J26

Y26

H_DSTBN#2

H_DSTBN#0

DSTBN0#

DSTBN2#

H26

AA26

H_DSTBP#0

H_DSTBP#2

DSTBP0#

DSTBP2#

H25

U22

H_DINV#0

DINV0#

DINV2#

H_DINV#2

H_D#16

H_D#17

H_D#18

H_D#19

H_D#20

H_D#21

H_D#22

H_D#23

H_D#24

H_D#25

H_D#26

H_D#27

H_D#28

H_D#29

H_D#30

H_D#31

N22

AE24

H_D#48

H_D#49

H_D#51

D16#

D48#

K25

AD24

D17#

D49#

H_D#50

H_D#52

H_D#53

H_D#54

H_D#55

H_D#57

P26

AA21

D18#

D50#

R23

AB22

D19#

D51#

L23

AB21

D20#

D52#

M24

AC26

D21#

D53#

L22

AD20

D22#

D54#

M23

AE22

D23#

D55#

H_D#56

H_D#58

H_D#59

H_D#60

H_D#61

H_D#63

P25

AF23

D24#

D56#

Layout notes

Z= 55 Ohm 0.5" MAX for GTLREF

P23

AC25

D25#

D57#

P22

AE21

D26#

D58#

T24

AD21

D27#

D59#

R24

AC22

D28#

D60#

L25

AD23

D29#

D61#

+1.05VS

H_D#62

T25

AF22

D30#

D62#

N25

AC23

D31#

D63#

L26

AE25

H_DSTBN#1

H_DSTBN#3

DSTBN1#

DSTBN3#

M26

AF24

H_DSTBP#1

DSTBP1#

DSTBP3#

H_DSTBP#3

1KR2F-3-GP

R19

N24

AC20

H_DINV#3

H_DINV#1

DINV1#

DINV3#

R19

CPU_GTLREF0

COMP0

COMP1

COMP2

COMP3

R23

27D4R2F-L1-GP

AD26

R26

GTLREF

COMP0

TEST1

TEST2

C23

MISC

U26

R24

54D9R2F-L1-GP

TEST1

COMP1

R67

27D4R2F-L1-GP

D25

AA1

TEST2

COMP2

R18

2KR2F-3-GP

C46

SC1KP50V2KX-1GP

C46

SC1KP50V2KX-1GP

CPU_TEST3

CPU_TEST5

R68

54D9R2F-L1-GP

C24

TEST3

COMP3

AF26

TEST4

AF1

TEST5

DPRSTP#

H_DPRSTP#

7,18,35

A26

H_DPSLP#

TEST6

DPSLP#

D24

H_DPW R#

DPWR#

B22

CPU_BSEL0

H_PW RGD

BSEL0

PWRGOOD

B23

CPU_BSEL1

BSEL1

SLP#

H_CPUSLP#

C21

AE6

CPU_BSEL2

PSI#

BSEL2

PSI#

Connect to V Core

BGA479-SKT6-GPU7

R25

1KR2J-1-GP

R25

1KR2J-1-GP

R70

1KR2J-1-GP

R70

1KR2J-1-GP

Layout Note:

Comp0, 2 connect with Zo=27.4 ohm, make

Comp1, 3 connect with Zo=55 ohm, make

TEST1

R26

1KR2J-1-GP

trace length shorter than 0.5" .

TEST2

R228

1KR2J-1-GP

Route the TEST3 and TEST5 signals through

a ground referenced Zo = 55-ohm trace

that ends in a via that is near a GND via

and is accessible through an oscilloscope connection.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (3 of 2 )

Size

Document Number

Rev

HBU16 1.2

Date:

Thursday, July 09, 2009

Sheet

+VCC_CORE

Please these outside socket

cavity on L8(North side Secondary)

U54D

4 OF 4

+VCC_CORE

Please these inside socket

cavity on L8(North side Secondary)

C408

C403

C442

C435

C426

C417

C409

C404

VSS

P21

VSS

A11

P24

VSS

A14

VSS

C147

C128

C97

C77

A16

VSS

A19

R22

VSS

A23

R25

VSS

AF2

VSS

+VCC_CORE

T23

VSS

+VCC_CORE

B11

T26

VSS

B13

VSS

B16

VSS

U54C

3 OF 4

Please these inside socket cavity on L8(South side Secondary)

B19

U21

VSS

B21

U24

VSS

+VCC_CORE

AB20

B24

VCC

VSS

AB7

VCC

VSS

A10

AC7

V22

VCC

VSS

+VCC_CORE

A12

AC9

C11

V25

VCC

VSS

A13

AC12

C14

VCC

VSS

C414

C441

C416

C425

C434

A15

AC13

C16

VCC

VSS

A17

AC15

C19

W23

VCC

VSS

A18

AC17

W26

VCC

VSS

A20

AC18

C83

C93

C104

C22

VCC

VSS

AD7

C25

VCC

VSS

AD9

Y21

VCC

VSS

B10

AD10

Y24

VCC

VSS

B12

AD12

AA2

VCC

VSS

B14

AD14

D11

AA5

VCC

VSS

B15

AD15

D13

AA8

VCC

VSS

B17

AD17

D16

AA11

VCC

VSS

B18

AD18

D19

AA14

VCC

VSS

+VCC_CORE

Please these inside socket

cavity on L8(North side Primary)

B20

AE9

D23

AA16

VCC

VSS

AE10

D26

AA19

VCC

VSS

C10

AE12

AA22

VCC

VSS

C12

AE13

Please these outside socket

cavity on L8(South side Secondary)

AA25

VCC

VSS

C13

AE15

AB1

VCC

VSS

C15

AE17

E11

AB4

VCC

VSS

C436

C114

C126

C430

C422

C133

C17

AE18

E14

AB8

VCC

VSS

C18

AE20

E16

AB11

VCC

VSS

AF9

E19

AB13

VCC

VSS

D10

AF10

E21

AB16

VCC

VSS

D12

AF12

E24

AB19

VCC

VSS

D14

AF14

AB23

VCC

VSS

D15

AF15

AB26

VCC

VSS

Please these inside socket

cavity on L8(South side Primary)

D17

AF17

F11

AC3

VCC

VSS

D18

AF18

F13

AC6

VCC

VSS

+1.05VS

AF20

F16

AC8

VCC

VSS

F19

AC11

VCC

VSS

E10

G21

AC14

VCC

VCCP

VSS

+VCC_CORE

E12

F22

AC16

VCC

VCCP

VSS

E13

F25

AC19

VCC

VCCP

VSS

E15

AC21

VCC

VCCP

VSS

E17

AC24

VCC

VCCP

VSS

TC14

ST220U2D5VBM-LGP

TC14

ST220U2D5VBM-LGP

E18

J21

G23

AD2

VCC

VCCP

VSS

E20

K21

G26

AD5

VCC

VCCP

VSS

M21

AD8

VCC

VCCP

VSS

C132

C125

C113

C103

C92

C82

N21

AD11

VCC

VCCP

VSS

F10

H21

AD13

VCC

VCCP

VSS

F12

R21

layout note: "1D5V_VCCA_S0"

as short as possible

H24

AD16

VCC

VCCP

VSS

F14

AD19

VCC

VCCP

VSS

F15

T21

AD22

VCC

VCCP

VSS

F17

J22

AD25

VCC

VCCP

VSS

+1.5VS

F18

V21

J25

AE1

CPU_GND1

VCC

VCCP

VSS

+1.5V_VCCA_S0

F20

W21

AE4

TP11

TPAD14-GP

VCC

VCCP

VSS

R225

0R0603-PAD

AA7

AE8

VCC

VSS

AA9

B26

K23

AE11

VCC

VCCA

VSS

AA10

C26

K26

AE14

VCC

VCCA

VSS

C383

C381

AA12

AE16

H_VID[6..0]

VCC

VSS

H_VID0

H_VID1

H_VID2

H_VID3

H_VID4

H_VID5

AA13

AD6

AE19

NCTF PIN

VCC

VID0

VSS

+VCC_CORE

AA15

AF5

L21

AE23

VCC

VID1

VSS

AA17

AE5

L24

AE26

CPU_GND2

VCC

VID2

VSS

Layout Note:

Place as close as possible to the CPU VCCA pin.

CPU_GND3

AA18

AF4

TP44

TPAD14-GP

VCC

VID3

VSS

TP12

TPAD14-GP

AA20

AE3

AF6

VCC

VID4

VSS

R56

100R2F-L1-GP-U

AB9

AF3

M22

AF8

VCC

VID5

VSS

AC10

AE2

H_VID6

M25

AF11

VCC

VID6

VSS

AB10

AF13

VCC

VSS

AB12

AF16

VCC

VSS

Connect to V Core

AB14

AF7

N23

AF19

VCC_SENSE

VCC

VCCSENSE

VSS

AB15

N26

AF21

VCC

VSS

CPU_GND4

AB17

A25

VCC

VSS

TP43

TPAD14-GP

AB18

AE7

Layout Note:

AF25

VSS_SENSE

VCC

VSSSENSE

VSS

VCCSENSE and VSSSENSE lines

R57

100R2F-L1-GP-U

should be of equal length.

BGA479-SKT6-GPU7

Layout Note:

Provide a test point (with

no stub) to connect a

differential probe

between VCCSENSE and

VSSSENSE at the location

where the two 54.9ohm

resistors terminate the

55 ohm transmission line.

+1.05VS

1 C145

1 C144

C69

1 C146

C68

C70

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Please these inside socket

cavity on L8(North side Secondary)

Title

CPU (3 of 3 )

Size

Document Number

Rev

HBU16 1.2

Date:

Thursday, July 09, 2009

Sheet

HP G60 COMPAQ CQ60 - WISTRON HBU16 1.2 - REV 1.pdf

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