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DS057: XC9572XL High-Performance CPLD Data Sheet
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XC9572XL High Performance
CPLD
DS057 (v2.0) April 3, 2007
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Product Specification
Features
• 5 ns pin-to-pin logic delays
• System frequency up to 178 MHz
• 72 macrocells with 1,600 usable gates
• Available in small footprint packages
- 44-pin PLCC (34 user I/O pins)
- 44-pin VQFP (34 user I/O pins)
- 48-pin CSP (38 user I/O pins)
- 64-pin VQFP (52 user I/O pins)
- 100-pin TQFP (72 user I/O pins)
- Pb-free available for all packages
• Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
• Advanced system features
- In-system programmable
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
• Pin-compatible with 5V-core XC9572 device in the
44-pin PLCC package and the 100-pin TQFP package
WARNING: Programming temperature range of
T A = 0° C to +70° C
Description
The XC9572XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
where:
MC HS = # macrocells in high-speed configuration
PT HS = average number of high-speed product terms
per macrocell
MC LP = # macrocells in low power configuration
PT LP = average number of low power product terms per
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual I CC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
© 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm .
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS057 (v2.0) April 3, 2007
1
Product Specification
cations and computing systems. It is comprised of four
54V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 5 ns. See Figure 2 for overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of I CC , the following equation may be
used:
I CC (mA) = MC HS (0.175*PT HS + 0.345) + MC LP (0.052*PT LP
+ 0.272) + 0.04 * MC TOG (MC HS +MC LP )* f
256427616.026.png
XC9572XL High Performance CPLD
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125
100
178 MHz
75
50
104 MHz
25
0
50
100
150
200
Clock Frequency (MHz)
DS057_01_010102
Figure 1: Typical I CC vs. Frequency for XC9572XL
3
JTAG
Controller
JTAG Port
1
In-System Programming Controller
54
Function
Block 1
Macrocells
1 to 18
I/O
18
I/O
I/O
I/O
54
Function
Block 2
18
I/O
Blocks
Macrocells
1 to 18
I/O
54
Function
Block 3
Macrocells
1 to 18
I/O
18
I/O
I/O
3
I/O/GCK
54
Function
Block 4
1
I/O/GSR
18
I/O/GTS
2
Macrocells
1 to 18
DS057_02_082800
Figure 2: XC9572XL Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
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www.xilinx.com
DS057 (v2.0) April 3, 2007
Product Specification
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XC9572XL High Performance CPLD
Absolute Maximum Ratings (2)
Symbol
Description
Value
Units
V CC
Supply voltage relative to GND
–0.5 to 4.0
V
V IN
Input voltage relative to GND (1)
–0.5 to 5.5
V
V TS
Voltage applied to 3-state output (1)
–0.5 to 5.5
V
T STG
Storage temperature (ambient) (3)
–65 to +150
o C
T J
Junction temperature
+150
o C
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA. External I/O voltage may not exceed V CCINT by 4.0V.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free
packages, see XAPP427 .
Recommended Operation Conditions
Symbol
Parameter
Min
Max
Units
V CCINT
Supply voltage for internal logic
and input buffers
Commercial T A = 0 o C to 70 o C
3.0
3.6
V
Industrial T A = –40 o C to +85 o C3.0
3.6
V
V CCIO
Supply voltage for output drivers for 3.3V operation
3.0
3.6
V
Supply voltage for output drivers for 2.5V operation
2.3
2.7
V
V IL
Low-level input voltage
0
0.80
V
V IH
High-level input voltage
2.0
5.5
V
V O
Output voltage
0
V CCIO
V
Quality and Reliability Characteristics
Symbol
Parameter
Min
Max
Units
T DR
Data Retention
20
-
Years
N PE
Program/Erase Cycles (Endurance)
10,000
-
Cycles
V ESD
Electrostatic Discharge (ESD)
2,000
-
Volts
DC Characteristic Over Recommended Operating Conditions
Symbol
Parameter
Test Conditions
Min
Max
Units
V OH
Output high voltage for 3.3V outputs
I OH = –4.0 mA
2.4
-
V
Output high voltage for 2.5V outputs
I OH = –500
μ
A
90% V CCIO
-
V
V OL
Output low voltage for 3.3V outputs
I OL = 8.0 mA
-
0.4
V
Output low voltage for 2.5V outputs
I OL = 500
μ
A
-
0.4
V
I IL
Input leakage current
V CC = Max; V IN = GND or V CC
-
±10
μ
A
I IH
I/O high-Z leakage current
V CC = Max; V IN = GND or V CC
-
±10
μ
A
I IH
I/O high-Z leakage current
V CC = Max; V CCIO = Max;
V IN = GND or 3.6V
-
±10
μ
A
V CC Min < V IN < 5.5V
-
±50
μ
A
C IN
I/O capacitance
V IN = GND; f = 1.0 MHz
-
10
pF
I CC
Operating supply current
(low power mode, active)
V IN = GND, No load; f = 1.0 MHz
20 (Typical)
mA
DS057 (v2.0) April 3, 2007
www.xilinx.com
3
Product Specification
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XC9572XL High Performance CPLD
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AC Characteristics
XC9572XL-5
XC9572XL-7
XC9572XL-10
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
T PD
I/O to output valid
-
5.0
-
7.5
-
10.0
ns
T SU
I/O setup time before GCK
3.7
-
4.8
-
6.5
-
ns
T H
I/O hold time after GCK
0
-
0
-
0
-
ns
T CO
GCK to output valid
-
3.5
-
4.5
-
5.8
ns
f SYSTEM
Multiple FB internal operating frequency
-
178.6
-
125.0
-
100.0
MHz
T PSU
I/O setup time before p-term clock input
1.7
-
1.6
-
2.1
-
ns
T PH
I/O hold time after p-term clock input
2.0
-
3.2
-
4.4
-
ns
T PCO
P-term clock output valid
-
5.5
-
7.7
-
10.2
ns
T OE
GTS to output valid
-
4.0
-
5.0
-
7.0
ns
T OD
GTS to output disable
-
4.0
-
5.0
-
7.0
ns
T POE
Product term OE to output enabled
-
7.0
-
9.5
-
11.0
ns
T POD
Product term OE to output disabled
-
7.0
-
9.5
-
11.0
ns
T AO
GSR to output valid
-
10.0
-
12.0
-
14.5
ns
T PAO
P-term S/R to output valid
-
10.5
-
12.6
-
15.3
ns
T WLH
GCK pulse width (High or Low)
2.8
-
4.0
-
4.5
-
ns
T APRPW
Asynchronous preset/reset pulse width
(High or Low)
5.0
-
6.5
-
7.0
-
ns
T PLH
P-term clock pulse width (High or Low)
5.0
-
6.5
-
7.0
-
ns
V TEST
R 1
Output Type
V CCIO
3.3V
2.5V
V TEST
3.3V
2.5V
R 1
320 Ω
250 Ω
R 2
360 Ω
660 Ω
C L
35 pF
35 pF
Device Output
R 2
C L
DS058_03_081500
Figure 3: AC Load Circuit
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DS057 (v2.0) April 3, 2007
Product Specification
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XC9572XL High Performance CPLD
Internal Timing Parameters
XC9572XL-5
XC9572XL-7
XC9572XL-10
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
Buffer Delays
T IN
Input buffer delay
-
1.5
-
2.3
-
3.5
ns
T GCK
GCK buffer delay
-
1.1
-
1.5
-
1.8
ns
T GSR
GSR buffer delay
-
2.0
-
3.1
-
4.5
ns
T GTS
GTS buffer delay
-
4.0
-
5.0
-
7.0
ns
T OUT
Output buffer delay
-
2.0
-
2.5
-
3.0
ns
T EN
Output buffer enable/disable delay
-
0
-
0
-
0
ns
Product Term Control Delays
T PTCK Product term clock delay
-
1.6
-
2.4
-
2.7
ns
T PTSR
Product term set/reset delay
-
1.0
-
1.4
-
1.8
ns
T PTTS Product term 3-state delay
-
5.5
-
7.2
-
7.5
ns
Internal Register and Combinatorial Delays
T PDI
Combinatorial logic propagation delay
-
0.5
-
1.3
-
1.7
ns
T SUI
Register setup time
2.3
-
2.6
-
3.0
-
ns
T HI
Register hold time
1.4
-
2.2
-
3.5
-
ns
T ECSU
Register clock enable setup time
2.4
-
2.6
-
3.0
-
ns
T ECHO Register clock enable hold time
1.4
-
2.2
-
3.5
-
ns
T COI
Register clock to output valid time
-
0.4
-
0.5
-
1.0
ns
T AOI
Register async. S/R to output delay
-
6.0
-
6.4
-
7.0
ns
T RAI
Register async. S/R recover before clock
5.0
7.5
10.0
ns
T LOGI Internal logic delay
-
1.0
-
1.4
-
1.8
ns
T LOGILP
Internal low power logic delay
-
5.0
-
6.4
-
7.3
ns
Feedback Delays
T F
Fast CONNECT II feedback delay
-
1.9
-
3.5
-
4.2
ns
Time Adders
T PTA
Incremental product term allocator delay
-
0.7
-
0.8
-
1.0
ns
T SLEW
Slew-rate limited delay
-
3.0
-
4.0
-
4.5
ns
DS057 (v2.0) April 3, 2007
www.xilinx.com
5
Product Specification
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