GPNE555.PDF

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GTM CORPORATION
ISSUED DATE :2005/08/10
REVISED DATE :2006/05/15B
G P N E 5 5 5 S I N G L E T I M E R
Description
The GPNE555 is a highly stable timer integrated circuit. It can be operated in Astable mode and Monostable
mode. With monostable operation, the time delay is controlled by one external and one capacitor. With a stable
operation, the frequency and duty cycle are accurately controlled with two external resistors and one capacitor.
Features
Ԧ High current driver capability (=200mA)
Ԧ Adjustable duty cycle
Ԧ Timing form Sec to Hours
Ԧ Turn off time less than 2Sec
Applications
Ԧ Precision timing
Ԧ Pulse generation
Ԧ Time delay generation
Package Dimensions
D
GAUGE PLANE
REF.
Min.
Millimeter
Max.
REF.
Min.
Millimeter
Max.
A
-
0.5334
c1
0.203
0.279
A1
0.381
-
D
9.017
10.16
A2
2.921
4.953
E
6.096
7.112
SEATING PLANE
b
b
0.356
0.559
E1
7.620
8.255
Z
Z
b1
0.356
0.508
e
2.540 BSC
SECTION Z - Z
b2
HE
1.143
1.778
-
10.92
b
e
DIP-8
b3
0.762
1.143
L
2.921
3.810
c
0.203
0.356
Block Diagram & Pin Configuration
GPNE555 Page: 1/5
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GTM CORPORATION
ISSUED DATE :2005/08/10
REVISED DATE :2006/05/15B
Absolute Maximum Ratings (Ta=25 к )
Parameter
Symbol
Value
Unit
Supply Voltage
V CC
16
V
Output Current
I O
200
mA
Power Dissipation
Pd
600
mW
Lead Temperature (10sec)
Tlead
300
к
Operating Temperature
Topr
0 ~ 70
к
Storage Temperature
Tstg
-65 ~ 150
к
Electrical Characteristics (T A =25 к V CC =5 ~ 15V)
Parameter
Symbol
Test Conditions
Min Typ. Max. Unit
Supply Voltage
V CC
4.5
-
16
V
Supply Current (Note 1)
I CC
V CC =5V, RL=
-
3
6
mA
V CC =15V, RL=
-
10
15
mA
Timing Error(monostable)
Initial Accurary (Note 1)
A CCUR R A =1k to 100k
-
1.0
-
%
Drift with Temperature Ϧ t/ Ϧ T C=0.1F
-
50
- ppm/ к
Drift with Supply Voltage
Ϧ t/ Ϧ V CC
-
0.1
-
%/V
Timing Error(astable)
Initial Accurary (Note 1)
A CCUR R A =1k to 100k
-
2.25
-
%
Drift with Temperature
Ϧ t/ Ϧ T C=0.1F
-
150
- ppm/ к
Drift with Supply Voltage
Ϧ t/ Ϧ V CC
-
0.3
-
%/V
Control Voltage
V C
V CC =15V
9.0 10.0 11.0
V
V CC =5V
2.6 3.33 4.0
V
Threshold Voltage
V TH
V CC =15V
9.2 10.0 10.8
V
V CC =5V
3.1 3.33 3.55
V
Threshold Current (Note 3)
I TH
-
0.1 0.25
A
Trigger Voltage
V tr
V CC =5V
1.1 1.67 2.2
V
V CC =15V
4.5
5
5.6
V
Trigger Current
I tr
V tr =0
-
-
2.0
A
Reset Voltage
V rst
0.4
0.7
1.0
V
Reset Current
I rst
-
0.1
0.4
mA
V CC =15V, I sink =10mA
-
0.06 0.25
Low Output Voltage
V OL
V CC =15V, I sink =50mA
-
0.3 0.75
V
V CC =5V, I sink =5mA
-
0.05 0.35
V CC =15V, I source =200mA
-
12.5
-
High Output Voltage
V OH
V CC =15V, I source =100mA
12.75 13.3 15
V
V CC =5V, I source =100mA
2.75 3.3
5
Reset Time of Output
t R
-
100
-
nSec
Fall Time of Output
t F
-
100
-
nSec
Discharge leakage Current
I LKG
-
20
100
nA
Note1: Supply current when output is high typically 1mA less at V CC =5V.
Note2: Tested at V CC =5V and V CC =15V.
Note3: This will determine the maximum value of RA+RB for 15V operation, the maximum total is R=20M, and for 5V operation the
maximum total is R=6.7M.
GPNE555 Page: 2/5
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GTM CORPORATION
ISSUED DATE :2005/08/10
REVISED DATE :2006/05/15B
Characteristics Curve
V CC = 15 V
GPNE555 Page: 3/5
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GTM CORPORATION
GPNE555 Page: 4/5
ISSUED DATE :2005/08/10
REVISED DATE :2006/05/15B
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GTM CORPORATION
ISSUED DATE :2005/08/10
REVISED DATE :2006/05/15B
Application Circuit
FLIP-FLOP
GPNE555
Application Notes
The application circuit shows astable mode configuration.
Pin 6 (Threshold) is tied to Pin 2 (Trigger) and Pin 4 (Reset) is tied to V CC (Pin 8). The external capacitor C1
of Pin 6 and Pin 2 charges through RA, RB and discharge through RB only. In the internal circuit of GPNE555,
one input of the upper comparator is at voltage of 2/3V CC (R1=R2=R3), another input is connected to Pin 6. As
soon as C1 is charging to higher than 2/3V CC , transistor Q1 is turned ON and discharge C1 to collector voltage
of transistor Q1. Therefore, the flip-flop circuit is reset and output is low. One input of lower comparator is at
voltage of 1/3V CC , discharge transistor Q1 turn off and C1 charges through RA and RB. Therefore, flip-flop
circuit is set output high.
That is, when C1 charges through RA and RB, output is high and when C1 discharge through RB, output is
low. The charge time (output is high) t1 is 0.693 (RA+RB) C1 and the discharge time (output is low) T2 is
0.693RB*C1.
Vcc- Vcc
In =0.693
T1=0.693*(RA+RB)*C1
Thus the total period time T is given by T2=0.693*RB*C1
Vcc- Vcc
T=T1+T2=0.693(RA+2RB)*C1.
Then the frequency of astable mode is given by
1
T (RA+2RB)*C1
1.44
The duty cycle is given by
D.C. = = .
RB
RA+2RB
portant Notice:
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of GTM.
GTM reserves the right to make changes to its products without notice.
GTM semiconductor products are not warranted to be suitable for use in life-support Applications, or systems.
GTM assumes no liability for any consequence of customer product design, infringement of patents, or application assistance.
Head Office And Factory:
Taiwan : No. 17-1 Tatung Rd. Fu Kou Hsin-Chu Industrial Park, Hsin-Chu, Taiwan, R. O. C.
TEL : 886-3-597-7061 FAX : 886-3-597-9220, 597-0785
China : (201203) No.255, Jang-Jiang Tsai-Lueng RD. , Pu-Dung-Hsin District, Shang-Hai City, China
TEL : 86-21-5895-7671 ~ 4 FAX : 86-21-38950165
GPNE555 Page: 5/5
1
3
2
1 3
f = =
T2
T
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