TDA9106.PDF

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LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
TDA9106
LOW COST DEFLECTION PROCESSOR
FOR MULTISYNC MONITORS
. SELF-ADAPTATIVE
PRELIMINARY DATA
. 150kHz MAXIMUM FREQUENCY
Combined with ST7275 Microcont roller family,
TDA9206 (Video prea mplifier) and STV942x
(On-Screen Display controller) the TDA9106
allows to built fully I 2 C bus controlled computer
display monitors, thus reducing the number of
exte rnal compo nents to a minimum value .
. X-RAY PROTECTION INPUT
. I 2 C CONTROLS : HORIZONTAL DUTY-CYCLE,
H-POSITION, FREE RUNNING FREQUENCY,
FREQUENCY GENERATOR FOR BURN-IN
MODE
VERTICAL
. GEOMETRY TRACKING WITH V-POS & AMP
. I 2 C CONTROLS :
V-AMP, V-POS, S-CORR, C-CORR
I 2 C GEOMETRY CORRECTIONS
. VERTICAL PARABOLA GENERATOR
(Pincushion, Keystone, Corner Correction,
Top/bottom Corner Correction Balance)
SHRINK42
(Plastic Package)
ORDER CODE : TDA9106
. HORIZONTAL AND VERTICAL DYNAMIC FO-
PIN CONNECTIONS
S/G
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
GND
SDA
SCL
5V
H/HVIN
HLOCKOUT
CUS (Horizontal Focus Amplitude, Horizontal
Focus Symmetry)
GENERAL
MOIRE
41
. SYNC PROCESSOR
. HOR. & VERT. SYNC OUTPUT FOR MCU
PLL1INHIB
PLL2C
HREF
HFLY
HGND
FC2
FC1
C0
R0
PLL1F
HLOCKCAP
HPOS
XRAY
HFOCUSCAP
HFOCUS
V CC
GND
HOUTEM
HOUTCOL
40
. HOR. & VERT. BLANKING OUTPUTS
39
. 12V SUPPLY VOLTAGE
38
. 8V REFERENCE VOLTAGE
37
. HOR. & VERT. LOCK UNLOCK OUTPUTS
36
HOUT
. READ/WRITE I 2 C INTERFACE
. HORIZONTAL MOIRE OR DAC OUTPUT
35
VSYNCOUT
TEST
34
33
VSYNCIN
VFOCUS
EWOUT
VFLY
VOUT
VDCOUT
VCAP
V REF
VAGCCAP
VGND
VBLKOUT
HBLKOUT
32
31
DESCRIPTION
The TDA9106 is a monolithic integrated circuit as-
sembled in 42 pins shrunk dual in line plastic pack-
age. This IC controls all the functions related to the
horizontal and vertical deflection in multimodes or
multi-frequency computer display monitors.
The internal sync processor, combined with the very
powerful geometry correction block are making the
TDA9106 suitable for very high performance moni-
tors with very few external components.
It is particularly well suited for high-end 15” and 17”
monitors.
30
29
28
27
26
25
24
23
22
November 1997
1/30
This is advance information on a new product now in development or undergoing evaluatio n. Details are subject to change without notice.
HORIZONTAL
. DUAL PLL CONCEPT
. 50 TO 165Hz AGC LOOP
. VERTICAL RAMP GENERATOR
. HORIZONTAL DYNAMIC PHASE
(Side Pin Balance & Parallelogram)
11038121.002.png
TDA9106
PIN CONNECTIONS
Pin
Name
Function
1
S/G
Sync on green input
2
MOIRE
Moire output
3
PLL1 INHIB
TTL-Compatible input for PLL1 inhibition
4
PLL2C
Second PLL Loop Filter
5
HREF
Horizontal Section Reference Voltage (to filter)
6
HFLY
Horizontal Flyback Input (positive polarity)
7
HGND
Horizontal Section Ground
8
FC2
VCO Low Threshold filtering Capacitor
9
FC1
VCO High Threshold filtering Capacitor
10
C0
Horizontal Oscillator Capacitor
11
R0
Horizontal Oscillator Resistor
12
PLL1F
First PLL Loop Filter
13
HLOCKCAP
First PLL Lock/Unlock Time Constant Capacitor
14
HPOS
Horizontal Centering Output (to filter)
15
XRAY
X-RAY protection input (with internal latch function)
16
HFOCUSCAP Horizontal Dynamic Focus Oscillator Capacitor
17
HFOCUS
Horizontal Dynamic Focus Output
18
V CC
Supply Voltage (12V Typ)
19
GND
General Ground (related to V CC )
20
HOUTEM
Horizontal Drive Output (internal transistor emitter)
21
HOUTCOL
Horizontal Drive Output (int. trans. open collector)
22
HBLKOUT
Horizontal Blanking Output (see activation table)
23
VBLKOUT
Vertical Blanking Output (see activation table)
24
VGND
Vertical Section Ground
25
VAGCCAP
Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator
26
V REF
Vertical Section Reference Voltage (to filter)
27
VCAP
Vertical Sawtooth Generator Capacitor
28
V DCOUT
Vertical Position Reference Voltage Output
29
VOUT
Vertical Ramp Output (with frequency independant amplitude and S or C Corrections if any)
30
VFLY
Vertical Flyback Input (positive polarity)
31
EWOUT
East/West Pincushion Correction Parabola Output (with Corner corrections if any)
32
VFOCUS
Vertical Dynamic Focus Output
33
VSYNCIN
TTL-compatible Vertical Sync Input (for separated H&V)
34
TEST
Not to be used - Test pin
35
VSYNCOUT
TTL Vertical Sync Output (Extracted VSYNC in case of S/G or TTL Composite HV Inputs)
36
HOUT
TTL Horizontal Sync Output (To be used for frequency measurement)
37
HLOCKOUT
First PLL Lock/Unlock Output (5V unlocked - 0V locked)
38
H/HVIN
TTL-compatible Horizontal Sync Input
39
5V
Supply Voltage (5V Typ.)
40
SCL
I 2 C-Clock input
41
SDA
I 2 C-Data input
42
GND
Ground (Related to 5V)
2/30
11038121.003.png
TDA9106
QUICK REFERENCE DATA
Parameter
Value
Unit
Horizontal Frequency
15 to 150
kHz
Autosynch Frequency (for given R0 and C0)
1 to 4.5
FH
±
Horizontal Sync Polarity Input
YES
Polarity Detection (on both Horizontal and Vertical Sections)
YES
TTL Composite Synch or Sync on Green
YES
Lock/Unlock Identification (on both Horizontal 1st PLL and Vertical Section)
YES
I 2 C Control for H-Position
±
10
%
XRay Protection
YES
I 2 C Horizontal Duty Adjust
30 to 60
%
I 2 C Free Running Adjustment
0.8 to 1.3
F0
Stand-by Function
YES
Two Polarities H-Drive Outputs
YES
Supply Voltage Monitoring
YES
PLL1 Inhibition Possibility
YES
Blanking Outputs (both Horizontal and Vertical)
YES
Vertical Frequency
35 to 200
Hz
Vertical Autosync (for 150nF)
50 to 165
Hz
Vertical S-Correction
YES
Vertical C-Correction
YES
Vertical Amplitude Adjustment
YES
Vertical Position Adjustment
YES
East/West Parabola Output
YES
Pin Cushion Correction Amplitude Adjustment
YES
Keystone Adjustment
YES
Corner and Corner Balance Adjustments
YES
Internal Dynamic Horizontal Phase Control
YES
Side Pin Balance Amplitude Adjustment
YES
Parallelogram Adjustment
YES
Tracking of Geometric Corrections
YES
Reference Voltage (both on Horizontal and Vertical)
YES
Dynamic Focus (both Horizontal and Vertical)
YES
I 2 C Horizontal Dynamic Focus Amplitude Adjustment
YES
I 2 C Horizontal Dynamic Focus Keystone Adjustment
YES
Type of Input Sync Detection (supplied by 5V Digital Supply)
YES
Horizontal Moiré Output
YES
I 2 C Controlled H-Moiré Amplitude
YES
Frequency Generator for Burn-in
YES
Fast I 2 C Read/Write
400
kHz
3/30
11038121.004.png
3
12
14
37
13
11
10
9
8
6
4
21
20
GND
19
PHASE/FREQUENCY
COMPARATOR
H-PHASE (7 bits)
HREF
5
V REF
VCO
PHASE
COMPARATOR
PHASE
SHIFTER
H-DUTY
(5 bits)
HOUT
BUFFER
HGND
7
Safe Freq.
2 bits
Free Running
5 bits
SAFETY
PROCESSOR
18
V CC
X-RAY
15
H-SAWTOOTH
GENERATOR
16
HFOCUS
CAP
VFLY
30
HBLKOUT
22
BLANKING
GENERATOR
LOCK/UNLOCK
IDENTIFICATION
Spin Bal
6 bits
Amp & Keyst
2 x 5 bits
X 2
VBLKOUT
23
X 2
17
HFOCUS
VSYNCOUT
35
MOIRE
PROCESSOR
5 BITS
2 MOIRE
HOUT
36
Key Bal
6 bits
S/G
1
SYNC INPUT
SELECT
(2 bits)
H/HVIN
38
SYNC
PROCESSOR
X
H-FLY
VSYNC
VSYNCIN
33
V REF
VGND
26
V REF
GEOMETRY
TRACKING
CORNER
CORRECTION
(2 x 6 bits)
24
6 bits
TEST
34
6 bits
6 bits
VPOS
7 bits
X 2
5V
39
RESET GENERATOR
SDA
41
S AND C
CORRECTION
VERTICAL
OSCILLATOR
RAMP GENERATOR
X 2
7 bits
31
EWOUT
SCL
40
I 2 C INTERFACE
X
VAMP
7 bits
GND
42
TDA9106
27
25
28
29
32
9106-02.EPS
11038121.005.png
TDA9106
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V CC
Supply Voltage (Pin 18)
13.5
V
V DD
Supply Voltage (Pin 39)
5.7
V
V IN
Max Voltage on Pin 6
Pins 15, 21, 22, 23
Pin 1
Pin 4
Pins 3, 33,34,37,38,40,41
Pin 16
Pins 8, 9, 10, 11, 12, 13, 14, 25, 27, 30
1.8
12
3.6
4
5
6
8
V
V
V
V
V
V
V
VESD
ESD susceptibility
Human Body Model,100pF Discharge through 1.5k
2
kV
W
EIAJ Norm,200pF Discharge through 0
W
300
V
T stg
Storage Temperature
-40, +150
o C
T j
Junction Temperature
+150
o C
T oper
Operating Temperature
0, +70
o C
THERMAL DATA
Symbol
Parameter
Value
Unit
R th (j-a) Junction-ambient Thermal Resistance
Max.
65
o C/W
SYNCHRO PROCESSOR
Operating Conditions
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Unit
HsVR
Horizontal Sync Input Voltage
Pin 38
0
5
V
MinD
Minimum Horizontal Input Pulses Duration
Pin 38
0.7
m
s
Mduty
Maximum Horizontal Input Signal Duty Cycle
Pin 38
25
%
VsVR
Vertical Sync Input Voltage
Pin 33
0
5
V
VSW
Minimum Vertical Sync Pulse Width
Pin 33
5
m
s
VSmD Maximum Vertical Sync Input Duty Cycle
Pin 33
15
%
VextM M a xi m um V e rt i ca l S yn c W i d t h on T T L
H/Vcomposite or S/G
Pins 1, 38
750
m
s
Electrical Characteristics (V DD =5V,T amb =25 o C)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Unit
VSGDC S/G Clamped DC Level
Pin 1, I 1 =-1
m
A
1
V
ISGbias Internal Diode Bias Current
Pin 1, V 1 = 1.6V
10
m A
VSGTh Slicing Level (see application design choice)
Pin 1
0.2
V
VINTH H o r iz on t al a n d V ert i cal I npu t V o lt a ge
(Pins 33,38)
Low Level
High Level
2.2
0.8
V
V
RIN
Horizontal and Vertical Pull-Up Resistor
Pins 33,38
200
k
W
VOut
Output Voltage (Pins 35,36,37)
Low level
High Level
0
5
V
V
TfrOut Falling and Rising Output CMOS Buffer
Pins 35,36,37
Cout = 20pF
100
ns
VHlock Horizontal 1st PLL Lock Output Status (Pin 37)
Locked
Unlocked
0
5
V
V
VoutT
Extracted Vsync Integration Time (% of TH) on
H/V Composite or S/G
Pin 35, C0 = 820pF
26
35
%
5/30
11038121.001.png

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