PCF8833_1 - PHILIPS.pdf
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INTEGRATED CIRCUITS
DATA SHEET
PCF8833
STN RGB - 132
132
3 driver
´
´
Objective specification
2003 Feb 14
Philips Semiconductors
Objective specification
STN RGB - 132
´
132
´
3 driver
PCF8833
CONTENTS
10
LIMITING VALUES
11
HANDLING
1
FEATURES
12
DC CHARACTERISTICS
2
GENERAL DESCRIPTION
13
AC CHARACTERISTICS
3
ORDERING INFORMATION
14
APPLICATION INFORMATION
4
BLOCK DIAGRAM
14.1
Supply and capacitor connection configuration
5
PINNING
15
MODULE MAKER PROGRAMMING
6
INSTRUCTIONS
15.1
V
LCD
calibration
6.1
Exit commands
15.2
Factory defaults
6.2
Function set
15.3
Seal bit
7
FUNCTIONAL DESCRIPTION
15.4
OTP architecture
15.5
Interface commands
7.1
MPU interfaces
15.6
Suggestion on how to calibrate V
LCD2
using
MMVOP
7.2
Display data RAM and access arbiter
7.3
Command decoder
15.7
Example of filling the shift register
7.4
Grey scale controller
15.8
Programming flow
7.5
Timing generator
15.9
Programming specification
7.6
Oscillator
7.7
Reset
16
INTERNAL PROTECTION CIRCUITS
7.8
LCD voltage generator and bias level generator
17
BONDING PAD INFORMATION
7.9
Column drivers, data processing and data
latches
18
TRAY INFORMATION
7.10
Row drivers
19
DATA SHEET STATUS
8
PARALLEL INTERFACE
20
DEFINITIONS
8.1
8080-series 8-bit parallel interface
21
DISCLAIMERS
9
SERIAL INTERFACE
9.1
Write mode
9.2
Read mode
2003 Feb 14
2
Philips Semiconductors
Objective specification
STN RGB - 132
´
132
´
3 driver
PCF8833
1
FEATURES
Analog supply voltage range for V
LCD
generation V
DD2
to V
SS2
:
–
·
·
Single chip LCD controller and driver
2.4 to 4.5 V.
132 rows and 396 column outputs (132
RGB)
·
´
·
Analog supply voltage range for reference voltage
generation V
DD3
to V
SS1
:
–
·
Low cross talk by Frame Rate Control (FRC)
·
4 kbyte colours (RGB) = 4 : 4 : 4 mode
2.4 to 3.5 V.
·
256 colours (RGB) = 3:3:2 mode using the 209 kbit
RAM and a Look-Up Table (LUT)
·
Display supply voltage range V
LCD
to V
SS1
:
–
3.8 to 20 V.
·
65 kbyte colours (RGB) = 5 : 6 : 5 mode using the
209 kbit RAM with dithering
·
Low power consumption; suitable for battery operated
systems
·
8 colours Power-save mode
·
CMOS compatible inputs
·
Display data RAM 132
´
132 (RGB) (4 kbyte colour)
·
Manufactured in silicon gate CMOS process
Interfaces:
–
·
·
Optimized layout for COF, Chip On Glass (COG) and
Transformer Coupled Plasma (TCP) assembly.
3-line serial interface
–
8-bit 8080 Intel CPU interface.
Display features:
–
·
2
GENERAL DESCRIPTION
Area scrolling
The PCF8833 is a single chip low power CMOS LCD
controller driver, designed to drive colour Super-Twisted
Nematic (STN) displays of 132 rows and 132 RGB
columns. All necessary functions for the display are
provided in a single chip, including display RAM which has
a capacity of 209 kbit (132
–
32-line partial Display mode
–
Software programmable colour depth mode
–
N-line inversion for low cross talk.
·
On-chip:
–
132). The PCF8833
uses the Multiple Row Addressing (MRA) driving
technique in order to achieve the best optical performance
at the lowest power consumption. The PCF8833 offers
2 types of microcontroller interfaces namely the
8080 system interface and the 3-line serial interface.
´
12-bit
´
Oscillator for display system, requires no external
components (external clock also possible)
–
Generation of V
LCD
–
Segmented temperature compensation of V
LCD
and
frame frequency.
·
Logic supply voltage range V
DD1
to V
SS1
:
–
1.5 to 3.3 V.
3
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
PCF8833U/2DA/1
-
chip with bumps in tray
-
2003 Feb 14
3
Philips Semiconductors
Objective specification
STN RGB - 132
´
132
´
3 driver
PCF8833
4
BLOCK DIAGRAM
C0 to C395
R0 to R131
handbook, full pagewidth
34 to 429
2 to 33, 430 to 461,
464 to 495, 733 to 768
713, 719
731, 732
729, 730
724 to 728
722, 723
720, 721
V
LCDIN2
V2H
V1H
VC
V1L
V2L
LCD BIAS
LEVEL
GENERATOR
ROW
DRIVERS
COLUMN DRIVERS
DATA PROCESSING
712
674 to 683
684 to 690
703 to 711
530 to 539
626 to 631
632 to 637
638 to 643
644 to 649
650 to 655
656 to 661
662 to 667
668 to 673
691 to 696
697 to 702
508 to 517
V
LCDSENSE
V
LCDOUT1
V
LCDIN1
V
LCDOUT2
V
DD2
C1
ORTHOGONAL
FUNCTION
GENERATOR
DATA LATCHES
496
RESET
RES
+
C1
-
LCD
VOLTAGE
GENERATOR
555
C2
+
OSC
OSCILLATOR
C2
-
DISPLAY DATA RAM
132
C3
+
C3
-
C4
TIMING
GENERATOR
´
132
´
12-bits
+
578
C4
-
T1
T2
T3
T4
T5
T6
T7
C5
+
GREYSCALE
CONTROLLER
577
C5
576
-
V
SS2
575
X AND Y RAM WRITE
ADDRESS COUNTER
DISPLAY ADDRESS
READ COUNTER
565 to 572
557 to 564
574
V
OTP(gate)
V
OTP(drain)
V
DD3
V
DD1
V
SS1
573
COMMAND
DECODER
ARBITER
625
525 to 529
519 to 524
498 to 507
PCF8833
256/64 KBYTES
TO 4 KBYTES
COLOUR
MAPPING
256
COLOUR
LUT
MPU INTERFACES
556
579, 624
518
549
551
550
552
553
554
548
547
545
543
541
546
544
542
540
497
CS/SCE RD
D/C/SCLK
PS0
PS2
SDOUT
D0/SDIN
D1
D2
D4
D6
TE
V
DD(tieoff)
V
SS(tieoff)
WR
PS1
D3
D5
D7
MGU910
Fig.1 Block diagram.
2003 Feb 14
4
Philips Semiconductors
Objective specification
STN RGB - 132
´
132
´
3 driver
PCF8833
5
PINNING
SYMBOL
PAD
TYPE
DESCRIPTION
R95 to R64
2 to 33
O
LCD row driver outputs
C0 to C395
34 to 429
O
LCD column driver outputs
R0 to R31
430 to 461
O
LCD row driver outputs
R63
to R32
464 to 495
O
LCD row driver outputs
RES
496
I
external reset; this signal will reset the device and must be applied to properly
initialize the chip (active LOW)
TE
497
O/I
tearing line (in Normal mode it is always an output)
V
SS1
498 to 507
PS
system ground
V
SS2
508 to 517
PS
system ground
CS/SCE
518
I
chip select parallel interface or serial chip enable (active LOW)
V
DD1
519 to 524
PS
logic supply voltage
V
DD3
525 to 529
PS
V
DD2
and V
DD3
are the supply voltage pins for the internal voltage generator
including the temperature compensation circuits; V
DD2
and V
DD3
can be
connected together but in this case care must be taken to respect the supply
voltage range (see Chapter 13); V
DD1
is used as the supply for the rest of the
chip. V
DD1
can be connected together with V
DD2
and V
DD3
but in this case care
must also be taken to respect the supply voltage range; see Chapter 13. V
DD2
and V
DD3
must not be applied before V
DD1.
If the internal voltage generator is not used, pins V
DD2
and V
DD3
must be
connected to V
DD1
.
V
DD2
530 to 539
PS
D7
540
I/O
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
D3
541
I/O
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
D6
542
I/O
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
D2
543
I/O
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
D5
544
I/O
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
D1
545
I/O
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
D4
546
I/O
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
D0/SDIN
547
I/O
8-bit parallel data or serial data input
S
DO
UT
548
O
serial
data outp
ut; in Parallel mode tie to V
DD1
, V
SS1
or D0
D/C
/SCLK
549
I
data/comm
and indicator parallel interface or serial clock
WR
550
I
write clock
parallel interface; in Serial mode tie to V
DD1
(active LOW)
RD
551
I
read clock parallel interface; in Serial mode tie to V
DD1
(active LOW)
PS0
552
I
set serial or parallel interface mode PS1 and PS2 must tied to either V
SS1
or
V
DD1
PS1
553
I
set serial or parallel interface mode PS1 and PS2 must tied to either V
SS1
or
V
DD1
PS2
554
I
set serial or parallel interface mode PS1 and PS2 must tied to either V
SS1
or
V
DD1
2003 Feb 14
5
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