TDA8425(1).pdf

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INTEGRATED CIRCUITS
DATA SHEET
TDA8425
Hi-fi stereo audio processor;
I 2 C-bus
Product specification
File under Integrated Circuits, IC02
October 1988
90960432.007.png
Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I 2 C-bus
TDA8425
GENERAL DESCRIPTION
The TDA8425 is a monolithic bipolar integrated stereo sound circuit with a loudspeaker channel facility, digitally
controlled via the I 2 C-bus for application in hi-fi audio and television sound.
Feature:
·
Source and mode selector for two stereo channels
·
Pseudo stereo, spatial stereo, linear stereo and forced mono switch
·
Volume and balance control
·
Bass, treble and mute control
·
Power supply with power-on reset
QUICK REFERENCE DATA
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage (pin 4)
V CC
10.8
12.0
13.2
V
Input signal handling
V l
2
-
-
V
Input sensitivity
full power at the output stage
V i
-
300
-
mV
Signal plus noise-to-noise ratio
(S+N)/N
-
86
-
dB
Total harmonic distortion
THD
-
0.05
-
%
Channel separation
a
-
80
-
dB
Volume control range
G
-
64
-
6
dB
Treble control range
G
- 12
-
12
dB
Bass control range
G
-
12
-
15
dB
PACKAGE OUTLINE
20-lead dual in-line; plastic (SOT146); SOT146-1; 1996 November 26.
October 1988
2
90960432.008.png 90960432.009.png 90960432.010.png 90960432.001.png 90960432.002.png
 
Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I 2 C-bus
TDA8425
October 1988
3
90960432.003.png
Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I 2 C-bus
TDA8425
PINNING
Fig.2 Pinning diagram.
FUNCTIONAL DESCRIPTION
Source selector
The input to channel 1 (CH1) and channel 2 (CH2) is determined by the source selector. The selection is made from the
following AF input signals:
·
IN 1 L (pin 18); IN1 R (pin 20)
or
·
IN2 L (pin 1); IN2 R (pin 3)
Mode selector
The mode selector selects between stereo, sound A and sound B (in the event of bilingual transmission) for OUT R and
OUT L.
Volume control and balance
The volume control consists of two stages (left and right). In each part the gain can be adjusted between +6 dB and
- 64 dB in steps of 2 dB. An additional step allows an attenuation of ³ 80 dB. Both parts can be controlled independently
over the whole range, which allows the balance to be varied by controlling the volume of left and right output channels.
Linear stereo, pseudo stereo, spatial stereo and forced mono mode (1)
It is possible to select four modes: linear stereo, pseudo stereo, spatial stereo or forced mono. The pseudo stereo mode
handles mono transmissions, the spatial stereo mode handles stereo transmissions and the forced mono can be used
in the event of stereo signals.
(1) During forced mono mode the pseudo stereo mode cannot be used.
October 1988
4
90960432.004.png 90960432.005.png
Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I 2 C-bus
TDA8425
Bass control
The bass control stage can be switched from an emphasis of 15 dB to an attenuation of 12 dB for low frequencies in
steps of 3 dB.
Treble control
The treble control stage can be switched from +12 dB to
-
12 dB in steps of 3 dB.
Bias and power supply
The TDA8425 includes a bias and power supply stage, which generates a voltage of 0.5
´
V CC with a low output
impedance and injector currents for the logic part.
Power-on reset
The on-chip power-on reset circuit sets the mute bit to active, which mutes both parts of the treble amplifier. The muting
can be switched by transmission of the mute bit.
I 2 C-bus receiver and data handling
serial clock) carry information between the devices connected to the bus. Both
SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull up resistor.
When the bus is free both lines are HIGH.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW. The set up and hold times are specified in AC
CHARACTERISTICS.
-
serial data, SCL
-
A HIGH-to-LOW transition of the SDA line while SCL is HIGH is defined as a start condition.
A LOW-to-HIGH transition of the SDA line while SCL is HIGH is defined as a stop condition.
The bus receiver will be reset by the reception of a start condition. The bus is considered to be busy after the start
condition.
The bus is considered to be free again after a stop condition.
Module address
Data transmission to the TDA8425 starts with the module address MAD.
Fig.3 TDA8425 module address.
October 1988
5
Bus specification
The TDA8425 is controlled via the 2-wire I 2 C-bus by a microcomputer.
The two wires (SDA
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