@@@F_Titel RS232-driven shift register @@@F_Text The circuit, which consists of only a few gates and a latched shift register, is eminently suitable for driving several outputs via a two-wire RS232 connection. An example is the 'stepper-motor control' elsewhere in this issue. It may also prove useful when, for instance, all the gates of a microcontroller are occupied. The Program was used to drive eight LEDs via the prototype. The RS232 interface must be set to 9600 baud, no parity, eight data bits, one stop bit. So, to send a bit via the RS232 bus, a data block of ten bits (eight data bits plus one stop bit plus one start bit) must be sent. A logic 1 is sent as FFhex, which is eight ones and a logic low is sent as 00hex, that is eight zeros. In the quiescent state, the output of the RS232 interface is -12 V. A logic 1 is represented by -12 V and a logic 0 by +12 V. The internal protection diodes in IC1, in conjunction with R1, limit the input voltage to about 600 mV. The DATA line (pin 2 of IC2) carries the same signal as the RS232 bus, but converted to 0 V (logic low) and +5 V (logic 1). A leading edge at the input of the circuit, such as that of the start bit of a new data block, causes a positive pulse at the input of IC1b, which then enables the Schmitt trigger. Capacitor C3 is then discharged via D1. During the discharge time, the output of IC1c is high. As soon as C3 is discharged, the output of IC1b goes high, whereupon C3 is charged again via R3. After about 530 ?s, the potential across C3 is high enough to trigger IC1c, whereupon the output changes from 1 to 0. The consequent trailing edge causes the input of IC1e, which is normally held high by R5, to become low. This in turn results in a leading edge at the CLK input of IC2, enabling the information on the DATA line to be written. The lower branch in the diagram (IC1d and IC1f, functions in a similar manner, but the time constant R4-C4 is about ten times as long. When for 5.16 ms no signal is sent over the RS232 line, the STROBE signal becomes active, whereupon the data in the shift register is latched to the output. As shown in the diagram, the circuit may be expanded by linking the carry out of IC2 to a second (and subsequent) register (IC3, IC4, ...). [Willaert - 974113] @@@F_Klickfont @@@Klickbild 11.EPS Circuit diagram @@@F_Text
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