54AC257.pdf

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July 1998
54AC257 • 54ACT257
Quad 2-Input Multiplexer with TRI-STATE ®
Outputs
General Description
The ’AC/’ACT257 is a quad 2-input multiplexer with
TRI-STATE outputs. Four bits of data from two sources can
be selected using a Common Data Select input. The four
outputs present the selected data in true (noninverted) form.
The outputs may be switched to a high impedance s tate by
placing a logic HIGH on the common Output Enable (OE) in-
put,
Features
n I CC and I OZ reduced by 50%
n Multiplexer expansion by tying outputs together
n Noninverting TRI-STATE outputs
n Outputs source/sink 24 mA
n ’ACT257 has TTL-compatible inputs
n Standard Military Drawing (SMD)
— ’AC257: 5962-88703
— ’ACT257: 5962-89689
allowing
the
outputs
to
interface
directly
with
bus-oriented systems.
Logic Symbols
IEEE/IEC
DS100286-1
DS100286-2
Pin Names
Description
S
Common Data Select Input
OE
TRI-STATE Output Enable Input
I 0a –I 0d
Data Inputs from Source 0
I 1a –I 1d
Data Inputs from Source 1
Z a –Z d
TRI-STATE Multiplexer Outputs
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
FACT ™ is a trademark of Fairchild Semiconductor Corporation.
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© 1998 National Semiconductor Corporation
DS100286
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Connection Diagrams
Functional Description
The ’AC/’ACT257 is quad 2-input multiplexer with
TRI-STATE outputs. It selects four bits of data from two
sources under control of a Common Data Select input. When
the Select input is LOW, the I 0x inputs are selected and when
Select is HIGH, the I 1x inputs are selected. The data on the
selected inputs appears at the outputs in true (noninverted)
form. The device is the logic implementation of a 4-pole,
2-position switch where the position of the switch is deter-
mined by the logic levels supplied to the Select input. The
logic equations for the outputs are shown below:
Z a = OE • (1 1a • S+I 0a • S)
Z b = OE • (1 1b • S+I 0b • S)
Z c = OE • (1 1c • S+I 0c • S)
Z d = OE • (1 1d • S+I 0d • S)
When the Output Enable (OE) is HIGH, the outputs are
forced to a high impedance state. If the outputs are tied to-
gether, all but one device must be in the high impedance
state to avoid high currents that would exceed the maximum
ratings. Designers should ensure the Output Enable signals
to TRI-STATE devices whose outputs are tied together are
designed so there is no overlap.
Pin Assignment for
DIP and Flatpak
DS100286-3
Pin Assignment for LCC
Truth Table
Output
Select
Data
Outputs
E nab le
Input
Inputs
OE
S
I 0
I 1
Z
H
X
X
X
Z
L
H
X
L
L
DS100286-4
L
H
X
H
H
L
L
L
X
L
L
L
H
X
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagram
DS100286-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V CC )
Recommended Operating
Conditions
Supply Voltage (V CC )
’AC
2.0V to 6.0V
−0.5V to +7.0V
’ACT
4.5V to 5.5V
DC Input Diode Current (I IK )
V I = −0.5V
Input Voltage (V I )
0VtoV CC
−20 mA
Output Voltage (V O )
0VtoV CC
V I = V CC +0.5V
+20 mA
Operating Temperature (T A )
54AC/ACT
DC Input Voltage (V I )
−0.5V to V CC +0.5V
−55˚C to +125˚C
DC Output Diode Current (I OK )
V O = −0.5V
Minimum Input Edge Rate (
D
V/
D
t)
−20 mA
’AC Devices
V IN from 30% to 70% of V CC
V CC @ 3.3V, 4.5V, 5.5V
V O = V CC +0.5V
+20 mA
DC Output Voltage (V O )
−0.5V to V CC +0.5V
125 mV/ns
DC Output Source or Sink Current
(I O )
Minimum Input Edge Rate (
D
V/
D
t)
± 50 mA
’ACT Devices
V IN from 0.8V to 2.0V
V CC @ 4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT ™ circuits outside databook specifications.
DC Characteristics for ’AC Family Devices
54AC
DC V CC or Ground Current
Per Output Pin (I CC or I GND )
± 50 mA
Storage Temperature (T STG )
−65˚C to +150˚C
Junction Temperature (T J )
CDIP
175˚C
T A =
Symbol
Parameter
V CC
Units
Conditions
(V)
−55˚C to +125˚C
Guaranteed
Limits
V OUT = 0.1V
V IH
Minimum High
3.0
2.1
Level Input
4.5
3.15
V
or V CC − 0.1V
Voltage
5.5
3.85
V OUT = 0.1V
V IL
Maximum Low
3.0
0.9
Level Input
4.5
1.35
V
or V CC − 0.1V
Voltage
5.5
1.65
I OUT = −50 µA
V OH
Minimum High
3.0
2.9
Level Output
4.5
4.4
V
Voltage
5.5
5.4
(Note 2)
V IN = V IL or V IH
3.0
2.4
−12 mA
4.5
3.7
V
I OH
−24 mA
5.5
4.7
−24 mA
I OUT = 50 µA
V OL
Maximum Low
3.0
0.1
Level Output
4.5
0.1
V
Voltage
5.5
0.1
(Note 2)
V IN = V IL or V IH
3.0
0.50
12 mA
4.5
0.50
V
I OL
24 mA
5.5
0.50
24 mA
± 1.0
V I = V CC , GND
I IN
Maximum Input
5.5
µA
Leakage Current
3
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DC Characteristics for ’AC Family Devices (Continued)
54AC
T A =
Symbol
Parameter
V CC
Units
Conditions
(V)
−55˚C to +125˚C
Guaranteed
Limits
V I (OE) = V IL ,V IH
I OZ
Maximum
± 10.0
V I = V CC , GND
TRI-STATE
5.5
µA
V O = V CC , GND
Leakage Current
V OLD = 1.65V Max
I OLD
(Note 3) Minimum
Dynamic Output
Current
5.5
50
mA
I OHD
5.5
−50
mA
V OHD = 3.85V Min
V IN = V CC
I CC
Maximum Quiescent
5.5
80.0
µA
Supply Current
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: I IN and I CC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V CC .
Note 5: I CC for 54AC @ 25˚C is identical to 74AC @ 25˚C.
DC Characteristics for ’ACT Family Devices
54ACT
T A =
Symbol
Parameter
V CC
Units
Conditions
(V)
−55˚C to +125˚C
Guaranteed
Limits
V OUT = 0.1V
V IH
Minimum High
Level Input
Voltage
4.5
2.0
V
5.5
2.0
or V CC − 0.1V
V IL
Maximum Low
Level Input
Voltage
4.5
0.8
V OUT = 0.1V
V
5.5
0.8
or V CC − 0.1V
I OUT = −50 µA
V OH
Minimum High
Level Output
Voltage
4.5
4.4
V
5.5
5.4
(Note 6)
V IN = V IL or V IH
4.5
3.70
V
I OH
−24 mA
5.5
4.70
−24 mA
I OUT = 50 µA
V OL
Maximum Low
Level Output
Voltage
4.5
0.1
V
5.5
0.1
(Note 6)
V IN = V IL or V IH
4.5
0.50
V
I OL
24 mA
5.5
0.50
24 mA
± 1.0
I IN
Maximum Input
5.5
µA
V I = V CC , GND
Leakage Current
± 10.0
V I = V IL ,V IH
I OZ
Maximum TRI-STATE
5.5
µA
V O = V CC , GND
Leakage Current
V I = V CC − 2.1V
I CCT
Maximum
5.5
1.6
mA
I CC /Input
V OLD = 1.65V Max
I OLD
(Note 7) Minimum
Dynamic Output
Current
5.5
50
mA
V OHD = 3.85V Min
I OHD
5.5
−50
mA
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DC Characteristics for ’ACT Family Devices (Continued)
54ACT
T A =
Symbol
Parameter
V CC
Units
Conditions
(V)
−55˚C to +125˚C
Guaranteed
Limits
V IN = V CC
I CC
Maximum Quiescent
5.5
80.0
µA
Supply Current
or GND
Note 6: All outputs loaded; thresholds on input associated with output under test.
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
Note 8: I CC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C.
AC Electrical Characteristics
54AC
T A = −55˚C
Symbol
Parameter
V CC
Units
(V)
to +125˚C
C L = 50 pF
(Note 9)
t PLH
Propagation Delay
3.3
1.0
11.0
ns
I n to Z n
5.0
1.0
8.0
t PHL
Propagation Delay
3.3
1.0
11.0
ns
I n to Z n
5.0
1.0
8.5
t PLH
Propagation Delay
3.3
1.0
14.5
ns
StoZ n
5.0
1.0
11.0
t PHL
Propagation Delay
3.3
1.0
14.5
ns
StoZ n
5.0
1.0
11.0
t PZH
Output Enable Time
3.3
1.0
13.0
ns
5.0
1.0
10.0
t PZL
Output Enable Time
3.3
1.0
11.0
ns
5.0
1.0
9.5
t PHZ
Output Disable Time
3.3
1.0
13.0
ns
5.0
1.0
11.0
t PLZ
Output Disable Time
3.3
1.0
10.5
ns
5.0
1.0
9.5
Note 9: Voltage Range 3.3 is 3.0V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics
54ACT
T A = −55˚C
Symbol
Parameter
V CC
Units
(V)
to +125˚C
C L = 50 pF
(Note 10)
t PLH
Propagation Delay
5.0
1.0
8.0
ns
I n to Z n
t PHL
Propagation Delay
5.0
1.0
9.5
ns
I n to Z n
t PLH
Propagation Delay
5.0
1.0
11.0
ns
StoZ n
t PHL
Propagation Delay
5.0
1.0
11.5
ns
StoZ n
t PZH
Output Enable Time
5.0
1.0
9.5
ns
5
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