TDF8704T.pdf
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Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
FEATURES
APPLICATIONS
·
8-bit resolution
·
General purpose high-speed analog-to-digital
conversion for extended temperature applications
·
Sampling rate up to 50 MHz
·
Automotive
·
Extended temperature range (
-
40 to +85
°
C)
·
RF, satellite and GPS (Global Positioning System)
·
High signal-to-noise ratio over a large analog input
frequency range (7.4 effective bits at 4.43 MHz full-scale
input and at f
clk
= 50 MHz)
·
Medical
·
General industrial
·
Binary 3-state TTL outputs
·
Digital video (VCR, TV and satellite).
·
Overflow/underflow 3-state TTL output
TTL compatible digital inputs
·
GENERAL DESCRIPTION
·
Low-level AC clock input signal allowed
The TDF8704T is an 8-bit high-speed analog-to-digital
converter (ADC) for general industrial applications. It
converts the analog input signal into 8-bit binary-coded
digital words at a maximum sampling rate of 50 MHz. All
digital inputs and outputs are TTL compatible, although a
low-level AC clock input signal is allowed.
·
Stable internal reference voltage regulator included
·
Power dissipation only 380 mW (typical)
·
Low analog input capacitance, no buffer amplifier
required
·
No sample-and-hold circuit required.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
CCA
analog supply voltage
4.75
5.0
5.25
V
V
CCD
digital supply voltage
4.75
5.0
5.25
V
V
CCO
output stages supply voltage
4.75
5.0
5.25
V
I
CCA
analog supply current
-
37
46
mA
I
CCD
digital supply current
-
23
35
mA
I
CCO
output stages supply current
-
16
21
mA
ILE
DC integral linear error
-
±
0.4
±
1
LSB
DLE
DC differential linearity error
-
±
0.2
±
0.5
LSB
AILE
AC integral linearity error
note 1
-
-
±
2
LSB
f
clk(max)
maximum clock frequency
50
-
-
MHz
P
tot
total power dissipation
-
380
535
mW
Note
1.
Full-scale sine wave (f
i
= 4.43 MHz; f
clk
= 50 MHz).
ORDERING INFORMATION
PACKAGE
SAMPLING
FREQUENCY
TYPE NUMBER
PINS
PIN POSITION
MATERIAL
CODE
TDF8704T/2
24
SO24L
plastic
SOT137-1
20 MHz
TDF8704T/4
24
SO24L
plastic
SOT137-1
40 MHz
TDF8704T/5
24
SO24L
plastic
SOT137-1
50 MHz
June 1994
2
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
BLOCK DIAGRAM
handbook, full pagewidth
V
CCA
CLK
V
CCD
CE
7
16
18
22
STABILIZER
CLOCK DRIVER
DEC
5
V
RT
TDF8704
9
12
D7
MSB
13
D6
14
D5
15
D4
V
I
8
analog
voltage input
ANALOG - TO - DIGITAL
CONVERTER
data outputs
LATCHES
TTL OUTPUTS
23
D3
24
D2
1
2
D1
D0
LSB
V
RB
19
4
V
CCO1
21
V
CCO2
OGND
20
OVERFLOW / UNDERFLOW
LATCH
11
overflow / underflow
output
TTL OUTPUT
output ground
17
DGND
6
AGND
MSA685
analog ground
digital ground
Fig.1 Block diagram.
June 1994
3
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
PINNING
SYMBOL
PIN
DESCRIPTION
D1
1
data output; bit 1
D0
2
data output; bit 0 (LSB)
n.c.
3
not connected
V
RB
4
reference voltage BOTTOM
(decoupling)
DEC
5
decoupling input (internal
stabilization loop decoupling)
handbook, halfpage
D1
1
24
D2
D0
2
23
D3
AGND
6
analog ground
n.c.
3
22
CE
V
CCA
7
analog supply voltage (+5 V)
V
RB
V
CCO2
V
I
8
analog input voltage
4
21
V
RT
9
reference voltage TOP (decoupling)
5
20
OGND
DEC
n.c.
10
not connected
V
CCO1
AGND
6
19
TDF8704
O/UF
11
overflow/underflow data output
V
CCA
V
CCD
7
18
D7
12
data output; bit 7 (MSB)
V
I
8
17
DGND
D6
13
data output; bit 6
V
RT
9
16
CLK
D5
14
data output; bit 5
10
15
D4
n.c.
D4
15
data output; bit 4
O/UF
11
14
D5
CLK
16
clock input
DGND
17
digital ground
12
D6
D7
13
V
CCD
18
digital supply voltage (+5 V)
MSA686
V
CCO1
19
supply voltage for output stages 1
(+5 V)
OGND
20
output ground
V
CCO2
21
supply voltage for output stages 2
(+5 V)
CE
22
chip enable input (TTL level input,
active LOW)
D3
23
data output; bit 3
Fig.2 Pin configuration.
D2
24
data output; bit 2
June 1994
4
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CCA
analog supply voltage
-
0.3
+7.0
V
V
CCD
digital supply voltage
-
0.3
+7.0
V
V
CCO
output stages supply voltage
-
0.3
+7.0
V
D
V
CC
supply voltage differences between V
CCA
and V
CCD
-
1.0
+1.0
V
D
V
CC
supply voltage differences between V
CCO
and V
CCD
-
1.0
+1.0
V
D
V
CC
supply voltage differences between V
CCA
and V
CCO
-
1.0
+1.0
V
V
I
input voltage
referenced to AGND
-
0.3
+7.0
V
V
clk(p-p)
AC input voltage for switching (peak-to-peak value)
referenced to DGND
-
V
CCD
V
I
O
output current
-
10
mA
T
stg
storage temperature
-
55
+150
°
C
T
amb
operating ambient temperature
-
40
+85
°
C
T
j
junction temperature
-
+150
°
C
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
UNIT
R
th j-a
thermal resistance from junction to ambient in free air
75
K/W
June 1994
5
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
CHARACTERISTICS (see Tables 1 and 2)
V
CCA
= V
7
to V
6
= 4.75 to 5.25 V; V
CCD
= V
18
to V
17
= 4.75 to 5.25 V; V
CCO
= V
19
and V
21
to V
20
= 4.75 to 5.25 V; AGND
and DGND shorted together; V
CCA
to V
CCD
=
-
0.25 to +0.25 V; V
CCO
to V
CCD
=
-
0.25 to +0.25 V;
V
CCA
to V
CCD
=
-
0.25 to +0.25 V; T
amb
=
-
40 to +85
°
C; typical readings taken at V
CCA
= V
CCD
= 5 V and T
amb
= 25
°
C;
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
V
CCA
analog supply voltage
4.75
5.0
5.25
V
V
CCD
digital supply voltage
4.75
5.0
5.25
V
V
CCO
output stages supply voltage
4.75
5.0
5.25
V
I
CCA
analog supply current
-
37
46
mA
I
CCD
digital supply current
-
23
35
mA
I
CCO
output stages supply current
all outputs LOW
-
16
21
mA
Inputs
C
LOCK INPUT
CLK (
REFERENCED TO
DGND)
V
IL
LOW level input voltage
0
-
0.8
V
V
IH
HIGH level input voltage
2.0
-
V
CCD
V
I
IL
LOW level input current
V
clk
= 0.4 V
-
400
-
-
m
A
I
IH
HIGH level input current
V
clk
= 2.7 V
100
A
-
-
m
V
clk
= V
CCD
-
-
300
m
A
Z
I
input impedance
f
clk
= 50 MHz
-
2
-
k
W
C
I
input capacitance
f
clk
= 50 MHz
-
4.5
-
pF
V
I
(
ANALOG INPUT VOLTAGE REFERENCED TO
AGDN;
SEE FIGS
3
AND
4
AND TABLE
1)
V
I(B)
input voltage (BOTTOM)
1.21
1.25
1.29
V
V
I(0)
input voltage
output code = 0
1.42
1.48
1.51
V
V
os(B)
offset voltage (BOTTOM)
V
I(0)
to V
I(B)
210
225
240
V
V
I(T)
input voltage (TOP)
3.37
3.46
3.58
V
V
I(255)
input voltage
output code = 255
3.14
3.22
3.30
V
V
os(T)
offset voltage (TOP)
V
I(T)
to V
I(255)
225
240
255
V
V
I(p-p)
input voltage amplitude
(peak-to-peak value)
1.69
1.74
1.79
V
I
L
load current on V
RT
and V
RB
-
300
-
+300
m
A
I
IL
LOW level input current
V
I
= 1.25 V
-
0
-
m
A
I
IH
HIGH level input current
V
I
= 3.46 V
40
150
400
m
A
Z
I
input impedance
f
i
= 4.43 MHz
-
10
-
k
W
C
I
input capacitance
f
i
= 4.43 MHz
-
14
-
pF
June 1994
6
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