A ZVS PWM Inverter With Active Voltage Clamping Using the Reverse Recovery Energy of the Diodes.pdf

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 10, OCTOBER 2005

2219

A ZVS PWM Inverter With Active Voltage Clamping

Using the Reverse Recovery Energy of the Diodes

Marcello Mezaroba, Denizar Cruz Martins, and Ivo Barbi

Abstract— This paper presents a zero-voltage-switching (ZVS)

pulsewidth modulated inverter with active voltage clamping using

only a single auxiliary switch. The structure is particularly simple

and robust. It is very attractive for single-phase high-power appli-

cations. Switching losses are reduced due to implementation of the

simple active snubber circuit that provides ZVS conditions for all

switches, including the auxiliary one. Its main features are: simple

modulation strategy, robustness, low weight and volume, low har-

monic distortion of the output current and high efﬁciency. The

principle of operation for steady-state conditions, mathematical

analysis and experimental results from a laboratory prototype are

presented.

Index Terms— Active clamping, inverters, soft commutation.

Fig. 1.

Proposed circuit.

I. I NTRODUCTION

M UCH effort has been exerted by researchers all over

widely known is the Undeland snubber [1]. This snubber pro-

vides good performance in the majority of its applications, but

is not capable of regenerating the energy lost in switching. To

try to minimize these losses, some works have considered mod-

iﬁcations to the Undeland snubber, aiming at the regeneration

of the energy lost in switching [2]–[4] and [5]. The active solu-

tions are already distinguished by the use of controlled switches

to obtain soft commutation. The main ones are those that use

conventional pulsewidth modulation (PWM), without the need

for special control circuits. One of these works is the auxiliary

resonant auxiliary resonant diode pole inverter (ARDPI) [6].

This topology matches the use of PWM modulation, with the

soft switching attained through a relatively simple circuit. On

the other hand, it needs a high current circulating in the circuit,

about 2.5 times the load current, raising the current stress in

the switches. A topology very similar to the previous one is the

auxiliary resonant pole inverter (ARPI) [7]. Theoretically, this

circuit reduces the current levels necessary for switching, but

it involves a complex control strategy. Another circuit found

in literature is the auxiliary resonant commutated pole inverter

(ARCPI) [8], [9], and [10]. This inverter has auxiliary switches

that are only turned on when the load current is not sufﬁcient to

effect the soft switching, causing the control circuit to become

very complex and dependent on the sensors.

Recently, some research was carried out using the reverse re-

covery energy from the diodes to obtain soft commutation in the

switches of the pre-regulated rectiﬁers with high power factor

[11] and [12].

In this paper, a zero-voltage-switching (ZVS) PWM inverter

with voltage clamping across the switches, using only a single

auxiliary switch, is presented. The proposed structure uses the

diode reverse recovery energy technique to obtain soft commu-

tation in all switches, such as the rectiﬁer shown in [12].

the world in an attempt to reduce harmonic distortion

and audible noise in the output of inverters. Their objectives

have been attained through an increase in inverter commutation

frequencies and an appropriate modulation strategy. These

measures have provided some beneﬁts, such as a reduction in

the weight and volume of the magnetic elements. However,

they have caused some difﬁculties due to the high commutation

losses in the switches and the appearance of electromagnetic

interference. These factors occur mainly in inverter topologies

that use the bridge inverter conﬁguration. At the moment that

the main switch turns on, the anti-parallel diode of the bridge

complementary switch begins its reverse recovery phase.

During this stage, the switches are submitted to a high current

ramp rate and a high peak-reverse recovery current .

Both contribute signiﬁcantly to increasing the commutation

losses and produce electromagnetic interference.

To solve this problem, diverse works have been developed

by the scientiﬁc community in recent years and can be divided

into two groups: passive techniques and active techniques.

The passive techniques are characterized by the absence of

controlled switches in the switching aid circuit, while the active

techniques are characterized by circuits that use controlled

switches.

Among

the

passive

solutions,

perhaps

the

most

Manuscript received May 28, 2004; revised September 15, 2004. This paper

was recommended by Associate Editor A. Ioinovici.

M. Mezaroba is with the Power Electronics Laboratory (LEPO), the State

University of Santa Catarina (UDES), 89223-100 Joinville, SC, Brazil (e-mail:

mezaroba@joinville.udesc.br).

D. C. Martins and I. Barbi are with the Power Electronics Institute (INEP),

the Federal University of Santa Catarina (UFSC), 88040-970 Florianópolis, SC,

Brazil (e-mail: denizar@inep.ufsc.br; ivobarbi@inep.ufsc.br).

Digital Object Identiﬁer 10.1109/TCSI.2005.852914

1057-7122/$20.00 © 2005 IEEE

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2220

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 10, OCTOBER 2005

Fig. 2. Operation stages. (a) First state (t0-t1). (b) (b) Second stage (t1-t2). (c) Third stage (t2-t3). (d) Fourth stage (t3-t4). (e) Fifth stage (t4-t5). (f) Sixth stage

(t5-t6). (g) Seventh stage (t6-t7). (h) Eighth stage (t7-t8). (i) Ninth stage (t8-t0).

II. P ROPOSED C IRCUIT

. At the end of this stage, the current through inductor

reaches its maximum value,

(Fig. 3)

The proposed circuit is shown in Fig. 1. It presents a

half-bridge inverter conﬁguration, where are the main

switches. The snubber circuit is formed by one switch ,

one small center-tapped inductor and one capacitor

. , and are the commutation capacitors. Capacitor

is responsible for the storage of the diode reverse recovery

energy and for the clamping of the voltage across the switches.

Inductors and are responsible for the control of the

during the diode reverse recovery time.

(1)

(2)

(3)

(4)

(5)

This stage was chosen to initiate the converter analysis because

it precedes the commutation process of the main switch,

,

during the half-cycle of operation. At time t0 current

becomes positive and increases linearly. At the end of the

ﬁrst stage this current is responsible for the soft commutation

process of .

Second Stage (t1-t2): This stage starts when auxiliary switch

is blocked. Current

III. O PERATION S TAGES ( FOR F IRST H ALF -C YCLE )

To simplify the analysis, the following assumptions are

made: the circuit operates in steady state; the components are

considered ideal; the voltage across capacitor

and the cur-

charges capacitor

from zero

rent through the output inductor

are considered constant

to

, and discharges

from

to zero .

during the switching period.

In the following paragraphs, the operation stage (Fig. 2) of

the ﬁrst positive half-cycle of the output current is described in

detail.

First Stage (t0–t1): At t0, switch is turned on. During

this interval, the output current, , is delivering energy to

source via diode . At the same time, additional current

circulates through the mesh, formed by

. During this stage the current,

, circulates through

the intrinsic capacitor of switch

(6)

where

is the maximum current through

. Thus

, and

(7)

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MEZAROBA et al. : ZVS PWM INVERTER WITH ACTIVE VOLTAGE CLAMPING

2221

Fig. 3.

Main waveforms.

(8)

of diode

. The auxiliary inductors limit the reverse recovery

(9)

(16)

(17)

(18)

(10)

Third Stage (t2-t3): At t2, the voltage across reaches zero

and is clamped by diode . At this moment, the voltage

is applied across inductors

(19)

and

and currents

and

decrease linearly. In this stage, switch

must

(20)

be turned on

Fifth Stage (t4-t5): This stage starts when diode

stops

(11)

(12)

(13)

conducting. Current

begins charging capacitor

from

zero to

and discharging

from

to zero

(21)

(14)

(22)

where

.

where

is the maximum negative current through

. So,

(15)

Fourth Stage (t3-t4): This stage begins when current

inverts its direction and ﬂows through switch . The turn-on

occurs at zero voltage. Current continues to decrease until

inverting its direction, which begins the reverse recovery phase

(23)

(24)

(25)

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2222

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 10, OCTOBER 2005

Sixth Stage (t5-t6): At t5, the voltage across capacitor

reaches zero and is clamped by diode . Currents and

increase, due to the application of voltage across in-

ductors and . In this stage, switch must be turned

on. It is important to emphasize that the drive time of switch

is estimated previously and kept constant during the en-

tire inverter operation range. So, the use of current sensor is not

necessary

(46)

For the second half-cycle, the operation stage is analogous and

can be described in an identical way.

The main operation stages are shown in Fig. 2. Fig. 3 shows

the main waveforms.

IV. M ATHEMATICAL A NALYSIS OF C OMMUTATION

To guarantee the ZVS conditions, it is necessary, in the second

stage, that the stored energy in inductor be

sufﬁcient to discharge capacitor and to charge . Thus, by

inspection of Fig. 3 (Interval t1–t2), the following condition can

be formulated:

(26)

(27)

(28)

(29)

(47)

(30)

where is the maximum current in and is maintained

constant during the switching period. The current must be

sufﬁcient to promote the charge and discharge of the commuta-

tion capacitors.

Assuming that

Seventh Stage (t6-t7): This stage begins when current

changes its direction and ﬂows through switch

. Current

continues to increase linearly

,wehave

(31)

(32)

(33)

(48)

It is necessary to know the clamping voltage behavior for the

design of the switches and capacitor .

In steady-state conditions, the clamping capacitor average

current must be zero . Thus

(34)

(35)

Eighth

Stage

(t7-t8): During

this

stage,

switch

is

blocked and the current through

inverts its direction and

ﬂows through diode

. Capacitor

charges itself from zero

to

and capacitor

discharges from

to zero

(49)

(36)

where is the switching period.

In relation to the switching period, the commutation time

is very short. Therefore, the following simpliﬁcations can be

made:

(37)

(38)

(39)

(50)

(51)

(40)

From (50) and (51), (49) can be re-written as follows:

(41)

Ninth Stage (t8-t0): This stage begins when the voltage

across capacitor reaches zero and is clamped by diode .

Current continues to increase. This stage ﬁnishes when

inverts its direction and ﬂows through auxiliary switch

, restarting the ﬁrst operation stage

(52)

Solving the integral equation, and considering

(42)

(43)

(44)

(53)

we have

(45)

(54)

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MEZAROBA et al. : ZVS PWM INVERTER WITH ACTIVE VOLTAGE CLAMPING

2223

Fig. 4.

Modulation strategy.

Considering that the load current is a sinusoidal function and is

in phase with the output voltage, then

Equation (63) shows the inverter duty cycle obtained from (58),

(59), and (62)

(63)

(55)

Combining (54), (55), and (63), we obtain the expression of the

snubber capacitor voltage,

where is the load impedance.

Fig. 4 shows some signals of the modulation strategy used to

drive the main switches.

The sawtooth waveform is lined on the left edge. This facili-

tates the synchronism between the auxiliary switch and the main

switches.

The converter output voltage is controlled by the amplitude

modulation factor , which is obtained through the relation

between the peak value of the sinusoidal reference signal and

the peak value of the sawtooth waveform

, given by

(64)

where is the peak reverse recovery current of the anti-parallel

diode, which can be given by [16]

(65)

(56)

represents the reverse recovery charge of the diode.

From the analysis of the current behavior in capacitor

, the

The inverter output voltage for a switching period can be ex-

pressed by

expression of current

can be obtained

(66)

(57)

Combining (64) with (66), and making some simpliﬁcations, we

obtain the expression that represents the evolution of current

From (57) we can obtain the duty cycle

, that is

(58)

(67)

The inverter output voltage for an output period is given by

To guarantee the ZVS condition in all load ranges, the minimum

value of current obtained from (67) must be greater than the

value obtained from (48).

(59)

where

is expressed by

V.

D ESIGN E XAMPLE

(60)

A. Input Data

V

bus voltage;

V RMS output voltage;

VA output power;

A

— Output Frequency

The maximum output voltage is given by

output current;

(61)

fs

kHz

switching frequency;

Hz

output frequency;

The RMS output voltage is obtained from

mH

load inductance;

load resistance;

modulation factor.

(62)

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