tms_27c010a_eprom_datascheet.pdf

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TMS27C010A 131 072 BY 8-BIT UV ERASABLE
TMS27PC010A 131 072 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS110C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
Organization...131072 by 8 Bits
J PACKAGE
( TOP VIEW )
Single 5-V Power Supply
Operationally Compatible With Existing
Megabit EPROMs
V PP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V CC
PGM
NC
A14
A13
A8
A9
A1 1
G
A 10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Industry Standard 32-Pin Dual-In-line
Package and 32-Lead Plastic Leaded Chip
Carrier
All Inputs / Outputs Fully TTL Compatible
Maximum Access / Minimum Cycle Time
V CC
10%
’27C/PC010A-10
±
100
ns
’27C / PC010A-12
120
ns
’27C / PC010A-15
150
ns
’27C / PC010A-20
200
ns
8-Bit Output For Use in
Microprocessor-Based Systems
Very High-Speed SNAP! Pulse
Programming
Power-Saving CMOS Technology
3-State Output Buffers
400-mV Minimum DC Noise Immunity With
Standard TTL Loads
Latchup Immunity of 250 mA on All Input
and Output Pins
No Pullup Resistors Required
Low Power Dissipation (V CC = 5.5 V)
– Active...165 mW Worst Case
– Standby...0.55 mW Worst Case
(CMOS-Input Levels)
Temperature Range Options
FM PACKAGE
( TOP VIEW )
4
3213231
30
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A1 1
G
A 10
E
DQ7
description
14
15 16 17 18 19 20
The TMS27C010A series are 131 072 by 8-bit
(1 048 576-bit), ultraviolet (UV) light erasable,
electrically programmable read-only memories
(EPROMs).
PIN NOMENCLATURE
A0 – A16
Address Inputs
The TMS27PC010A series are 131 072 by 8-bit
(1 048 576-bit), one-time programmable (OTP)
electrically programmable read-only memories
(PROMs).
D Q0 – DQ7
Inputs (programming) / Outputs
E
Chip Enable
G
Output Enable
GND
Ground
NC
No Internal Connection
PGM
Program
V CC
5-V Power Supply
13-V Power Supply †
V PP
† Only in program mode
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright W 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
•
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TMS27C010A 131 072 BY 8-BIT UV ERASABLE
TMS27PC010A 131 072 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS110C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
description (continued)
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs ( including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pullup resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The TMS27C010A EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C010A is also offered with two choices of
temperature ranges, 0
°
C to 70
°
C (JL suffix) and – 40
°
C to 85
°
C (JE suffix). See Table 1.
The TMS27PC010A OTP PROM is offered in a 32-pin, plastic leaded chip carrier package using 1,25-mm
(50-mil) lead spacing ( FM suffix). The TMS27PC010A is offered with two choices of temperature ranges, 0
°
C
to 70
°
C ( FML suffix) and – 40
°
C to 85
°
C (FME suffix). See Table 1.
Table 1. Temperature Range Suffixes
EPROM
AND
OTP PROM
SUFFIX FOR OPERATING FREE-
AIR TEMPERATURE RANGES
0 ° C to 70 ° C
– 40 ° C to 85 ° C
TMS27C010A-xxx
JL
JE
TMS27PC010A-xxx
FML
FME
These EPROMs and OTP PROMs operate from a single 5-V supply ( in the read mode), thus are ideal for use
in microprocessor-based systems. One other 13-V supply is needed for programming. All programming signals
are TTL level. These devices are programmable using the SNAP! Pulse programming algorithm. The SNAP!
Pulse programming algorithm uses a V PP of 13 V and a V CC of 6.5 V for a nominal programming time of thirteen
seconds. For programming outside the system, existing EPROM programmers can be used. Locations can be
programmed singly, in blocks, or at random.
operation
The seven modes of operation are listed in Table 2. The read mode requires a single 5-V supply. All inputs are
TTL level except for V PP during programming (13 V for SNAP! Pulse), and 12 V on A9 for signature mode.
Table 2. Operation Modes
MODE †
FUNCTION
OUTPUT
DISABLE
PROGRAM
INHIBIT
READ
STANDBY
PROGRAMMING
VERIFY
SIGNATURE MODE
E
V IL
V IL
V IH
V IL
V IL
V IH
V IL
G
V IL
V IH
X
V IH
V IL
X
V IL
PGM
X
X
X
V IL
V IH
X
X
V PP
V CC
V CC
V CC
V PP
V PP
V PP
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V H ‡
V H ‡
A9
X
X
X
X
X
X
A0
X
X
X
X
X
X
V IL
V IH
CODE
DQ0 – DQ7
Data Out
Hi-Z
Hi-Z
Data In
Data Out
Hi-Z
MFG
DEVICE
97
D6
† X can be V IL or V IH .
‡ V H = 12 V
±
0.5 V.
•
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TMS27C010A 131 072 BY 8-BIT UV ERASABLE
TMS27PC010A 131 072 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS110C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
read / output disable
When the outputs of two or more TMS27C010As or TMS27PC010As are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from c om peti ng outputs of the
other devices. To read the output of a single device, a low-level signal is applied to the E and G pins. All other
devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins.
latchup immunity
Latchup immunity on the TMS27C010A and TMS27PC010A is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices
are interfaced to industry standard TTL or MOS logic devices. The input / output layout approach controls
latchup without compromising performance or packing density.
power down
Active I CC supply current can be reduced fr om 30 mA to 500
m
A by applying a high TTL input on E and to
100
m
A by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state.
erasure (TMS27C010A)
Before programmig, the TMS27C010A EPROM is erased by exposing the chip through the transparent lid to
a high intensity UV light (wavelength 2537 Å). The recommended minimum exposure dose (UV intensity
×
s/cm 2 . A typical 12-mW / cm 2 , filterless UV lamp erases the device in 21 minutes. The
lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state.
Normal ambient light contains the correct wavelength for erasure, therefore, when using the TMS27C010A, the
window must be covered with an opaque label. After erasure (all bits in logic high state), logic lows are
programmed into the desired locations. A programmed low can be erased only by UV light.
exposure time) is 15-W
V
initializing (TMS27PC010A)
The one-time programmable TMS27PC010A PROM is provided with all bits in the logic high state, then logic
lows are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
SNAP! Pulse programming
The TMS27C010A and TMS27PC010A are programmed using the TI SNAP! Pulse programming algorithm
illustrated by the flowchart in Figure 1, which programs in a nominal time of thirteen seconds. Actual
programming time varies as a function of the programmer used.
The SNAP! Pulse programming algorithm uses an initial pulse of 100 microseconds (
s) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-
m
s
m
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when V PP = 13 V, V CC = 6.5 V, E = V IL , G = V IH . Data is presented in parallel
(eight bits) on pins DQ0 through DQ7. Once addresses and data are stable, PGM is pulsed low.
More than one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with
V CC = V PP = 5 V
±
10%.
program inhibit
Programming can be inhibited by maintaining a high level input on the E or PGM pins.
program verify
Programmed bits can be verified with V PP = 13 V when G = V IL , E = V IL , and PGM = V IH .
•
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TMS27C010A 131 072 BY 8-BIT UV ERASABLE
TMS27PC010A 131 072 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS110C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
Start
Address = First Location
Program
Mode
V CC = 6.5 V ± 0.25 V, V PP = 13 V ± 0.25 V
Program One Pulse = t w = 100 m s
Increment Address
No
Last
Address?
Yes
Address = First Location
X = 0
Program One Pulse = t w = 100
m
s
No
Fail
Increment
Address
Verify
One Byte
X = X + 1
X = 10?
Interactive
Mode
Pass
No
Last
Address?
Yes
Yes
V CC = V PP = 5 V
±
0.5 V
Device Failed
Compare
All Bytes
to Original
Data
Fail
Final
Verification
Pass
Device Passed
Figure 1. SNAP! Pulse Programming Flowchart
•
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TMS27C010A 131 072 BY 8-BIT UV ERASABLE
TMS27PC010A 131 072 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS110C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 (pin 26) is forced to 12 V. Two identifier bytes are accessed by toggling A0. All other
addresses must be held low. The signature code for these devices is 97D6. A0 low selects the manufacturer’s
code 97 ( Hex), and A0 high selects the device code D6 (Hex), as shown in Table 3.
Table 3. Signature Mode
PINS
IDENTIFIER †
IDENTIFIER †
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
HEX
MANUFACTURER CODE
V IL
1
0
0
1
0
1
1
1
97
DE V IC E CODE
V IH
1
1
0
1
0
1
1
0
D6
† E = G = V IL , A1 – A8 = V IL , A9 = V H , A10 – A16 = V IL , V PP = V CC .
logic symbol ‡
EPROM 131 072 × 8
12
0
A0
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
22
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A1 6
E
13
A
_
A
DQ0
14
15
17
18
19
20
_
A
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
_
A
0
131 071
_
A
A
_
A
_
A
_
A
21
DQ7
_
16
[PWR DOWN]
&
EN
24
G
‡ This symbol is in accordance with ANSI / IEEE Std 91-1984 and IEC
Publication 617-12. J package illustrated.
•
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