Basic ESD And IO Design.pdf

BASIC ESD AND

I/O DESIGN

SANJAY DABRAL

TIMDTHY MALONEY

Intel Corporation

Santa Clara, California

A Wiley Interscience Publication

JOHN WILEY & SONS, INC.

New York ! Chichester { Weinheim I Brisbane I Singapore I Toronto

This book is printed on acid-free paper. §

Published simultaneously in Canada

No part of this publication may be reproduced, stored in a retrieval system or transmitted in any

form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise,

except as permitted under Sections 107 or 108 of the 1976 United States Copyright Act, without

either the prior written pennission of the Publisher, or authorization through payment of the

appropriate per-copy fee to the Copyright Clearance Center, 221 Rosewood Drive, Danvers, MA

01923, (508) 750-8400, fax (508) 750-4744. Requests to the Publisher for permission should be

addressed to the Permissions Department, John Wiley & Sons, Inc., 605 Third Avenue, New York,

NY 10158-0012, (212) 850-6011, fax (212) 850-6008, E-Mail: PERMREQ @ WILEY.COM

Library Cif Congress Calaloging-in-Publiculion Dala

Dabral, Sanjay

Basic ESD and I/O design / Sanjay Dabral and Timothy Maloney.

p. CIIl.

"A Wiley-Intersciencepublication."

Includes bibliographical references and index.

ISBN 0-471-25359-6 (alk. paper)

I. Integrated circuits-Very largescale integration-protection.

2. Electroniccireuit design. 3_ Electric discharges. 4. Static

eliminators. I. Maloney, Timothy J

TK7874.75.D33 1998

621.39'5----dc21

97-32241

Printed in the United States of America.

1098765432

CONTENTS

1. INTRODUCTION

1.1. Historical Perspective / I

1.2. Nature of ESD and Approximating Models I 2

1.2.1. ESD Relevant to Semiconductor Chips I 2

1.2.2. ESD-Related Failures I 3

1.3. ESD Issues in the Future I 4

1.3.1. I/O Pin Trends and Sensitivity of Increased

Technology I 5

1.3.2. Increased Number of Technologies! 7

1.3.3. Other Complications / 9

1.4. Solutions I 10

1.5. Outline of the Book / 12

1.6. Summary I 14

References ! 14

2. ESD PROTECTION METHODOLOGY

2.1. Additional Issues Due to ESn I 17

2.2. Devices for ESD Protection I 21

2.2.1. Thick-Field-Oxide (TFO) Clamps / 21

2.2.2. Grounded-Gate NMOS (GGNMOS) / 22

2.2.3. Silicon-Controlled Rectifier (SCR) / 23

2.2.4. Medium-Voltage Triggered SCR (MVTSCR) ! 25

2.2.5. Low-Voltage Triggered SCR (LVTSCR) / 25

2.2.6. Bimodal SCR ! 27

2.2.7. Gate-Coupled NMOS (GCNMOS) I 31

2.2.8. Punchthrough-Induced Protection Element (PIPE) j 32

2.2.9. Spark Gap / 35

2.2.10. Zener Clamps / 36

2.2.11. Double-Implant Field Inversion Device in Well

(DIFIDW) I 37

2.3. Electrothermal Simulation ! 38

2.4. Non-Breakdown Devices / 38

2.4.1. Diodes! 38

2.4.1.1. Cascaded Diodes! 40

2.4.2. MOSFETs / 43

2.5. Current Path Construction I 45

2.5.1. I/O Pad Segment / 47

2.5.1.1. Dual-Diode Based j 47

2.5.1.2. BieMOS BJT Based j 54

2.5.1.3. MOS Based! 56

2.6. Power Supply Coupling Segment I 57

2.6.1. Diode Based / 57

2.6.2. MOS Based! 61

2.7 vcc-to-V ss Core Clamps j 61

2.7.1. MOS Based j 61

2.7.2. Diode Clamps j 62

2.7.3. Cantilevered Diode j 68

2.8. CDM Guidelines j 71

2.9. Summary j 79

References j 80

3. ADDITIONAL ESD CONSIDERATIONS

3.1. Capacitor Benefits in Stress Reduction j 84

3.2. Packaging Effects on ESD I 86

3.2.1. Conventional Packaging I 86

3.2.2. Multichip Modules j 90

3.3. Small-Chip ESD Issues I 93

3.4. Benefits of Distributed Clamps I 95

3.5. Predriver Designs j 96

vii

3.6. Antenna Diode Issues / 99

3.7. Hot-Electron Interactions / 103

3.8. Latchup Issues / 105

3.9. Silicon-on-Insulator ESD Protection / 107

3.10. Summary / 109

References / 110

4. CIRCUITS

4.1. Transmission Line Phenomena / 113

4.2. Series and Parallel Termination / 119

4.3. CMOS I/O / 121

4.4. Gunning Transceiver Logic (GTL) I/O / 126

4.5. Bus Timing Considerations / 130

4.5.1. Common Clock Transfers / 130

4.5.2. Cotransmitted Clock (CTC) / 135

4.5.3. Pulse Width Modulation Scheme / 139

4.6. Topology Effects / 140

4.7. Bidirectional Signaling / 148

4.8. Compensation Schemes / 151

4.9. Analog Compensation / 153

4.10. Digital Compensation / 158

4.11. Frequency-Based Compensation / 161

4.12. Simultaneous Switching Output Noise / 162

4.12.1. Design for SSO Reduction / 168

4.12.1.1. Predriver Skewing / 168

4.12.1.2. NP-Inverted Stack Driver / 169

4.12./.3. Differential Signaling / 172

4.12.1.4. SSO Reduction Using Packaging

Options / 172

4.12.1.5. SSO Reduction Using Low-Weight

Coding / 173

4.13. System Modeling / 174

4.14. I/O Information on the Internet / 178

4.15. Summary j 179

References / 180

113

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika: