74LVC125A.pdf

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74LVC125A Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
INTEGRATED CIRCUITS
DATA SHEET
74LVC125A
Quad buffer/line driver with 5 V
tolerant input/outputs; 3-state
Product specification
Supersedes data of 2002 Mar 08
2003 May 07
203812682.051.png
Philips Semiconductors
Product specification
Quad buffer/line driver with 5 V tolerant input/outputs;
3-state
74LVC125A
FEATURES
DESCRIPTION
·
5 V tolerant inputs/outputs for interfacing with 5 V logic
The 74LVC125A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices.
In 3-state operation, outputs can handle 5 V.
·
Wide supply voltage range from 1.2 to 3.6 V
·
CMOS low power consumption
·
Direct interface with TTL levels
·
Inputs accept voltages up to 5.5 V
The 74LVC125A consists of four non-inverting buffers/line
drivers with 3-state outpu ts ( nY) which are con trolled by
the output enable input (nOE). A HIGH at nOE causes the
outputs to assume a high-impedance OFF-state.
·
Complies with JEDEC standard no. 8-1A
·
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
·
Specified from
-
40 to +85
°
C and
-
40 to +125
°
C.
QUICK REFERENCE DATA
GND = 0 V; T amb =25
C; t r =t f £
2.5 ns.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t PHL /t PLH
propagation delay nA to nY
C L = 50 pF; V CC = 3.3 V 2.4
ns
C I
input capacitance
4.0
pF
C PD
power dissipation capacitance per gate V CC = 3.3 V;
notes 1 and 2
12
pF
Notes
1. C PD is used to determine the dynamic power dissipation (P D in
m
W).
P D =C PD ´
V CC 2
´
f i ´
N+
S
(C L ´
V CC 2
´
f o ) where:
f o ) = sum of the outputs.
2. The condition is V I = GND to V CC .
f i = input frequency in MHz;
f o = output frequency in MHz;
C L = output load capacitance in pF;
V CC = supply voltage in Volts;
N = total load switching outputs;
S
(C L ´
V CC 2
´
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
TEMPERATURE RANGE
PINS
PACKAGE
MATERIAL
CODE
74LVC125AD
-
40 to +125
°
C
14
SO14
plastic
SOT108-1
74LVC125ADB
- 40 to +125 ° C
14
SSOP14
plastic
SOT337-1
74LVC125APW
-
40 to +125
°
C
14
TSSOP14
plastic
SOT402-1
74LVC125ABQ
-
40 to +125
°
C
14
DHVQFN14
plastic
SOT762-1
2003 May 07
2
°
203812682.062.png 203812682.069.png
Philips Semiconductors
Product specification
Quad buffer/line driver with 5 V tolerant input/outputs;
3-state
74LVC125A
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
nOE
nA
nY
L
L
L
L
H
H
H
X
Z
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
PINNING
PIN
SYMBOL
DESCRIPTION
1
1OE
data enable input (active LOW)
2
1A
data input
1OE
1
14
V CC
3
1 Y
data output
1A
2
13
4OE
4
2OE
data enable input (active LOW)
1Y
3
12
4A
5
2A
data input
2OE
4
125
11
4Y
6
2Y
data output
2A
5
10
3OE
7
GND
ground (0 V)
8
3Y
data output
2Y
6
9
3A
9
3 A
data input
GND
7
8
3Y
10
3OE
data enable input (active LOW)
MNA226
11
4Y
data output
12
4 A
data input
13
4OE
data enable input (active LOW)
Fig.1 Pin configuration SO14 and (T)SSOP14.
14
V CC
supply voltage
2003 May 07
3
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Philips Semiconductors
Product specification
Quad buffer/line driver with 5 V tolerant input/outputs;
3-state
74LVC125A
handbook, halfpage
1OE V CC
handbook, halfpage
2
1A
1Y
3
1
14
1A
2
13
4OE
1
1OE
1Y
3
12
4A
5
2A
2Y
6
4
2OE
2OE
4
GND (1)
11
4Y
9
3A
3Y
8
2A
5
10
3OE
10
3OE
2Y
6
9
3A
12
4A
4Y
11
7
8
13
4OE
GND
3Y
Top view
MCE181
MNA228
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.2 Pin configuration DHVQFN14.
Fig.3 Logic symbol.
handbook, halfpage
2
1
3
1
EN1
5
6
handbook, halfpage
4
nA
nY
9
8
10
nOE
MNA227
12
11
13
MNA229
Fig.4 Logic symbol (IEEE/IEC).
Fig.5 Logic diagram.
2003 May 07
4
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Philips Semiconductors
Product specification
Quad buffer/line driver with 5 V tolerant input/outputs;
3-state
74LVC125A
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V CC
supply voltage
for maximum speed performance
2.7
3.6
V
for low voltage applications
1.2
3.6
V
V I
input voltage
0
5.5
V
V O
output voltage
output HIGH or LOW state
0
V CC
V
output 3-state
0
5.5
V
T amb
operating ambient temperature
-
40
+125
°
C
t r ,t f
input rise and fall times
V CC = 1.2 to 2.7 V
0
20
ns/V
V CC = 2.7 to 3.6 V
0
10
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V CC
supply voltage
-
0.5
+6.5
V
I IK
input diode current
V I <0
-
- 50
mA
V I
input voltage
note 1
-
0.5
+6.5
V
I OK
output diode current
V O >V CC or V O <0
-
±
50
mA
V O
output voltage
output HIGH or LOW state; note 1
-
0.5
V CC + 0.5 V
output 3-state; note 1
- 0.5
+6.5
V
I O
output source or sink current
V O = 0 to V CC
-
±
50
mA
I CC , I GND V CC or GND current
-
±
100
mA
T stg
storage temperature
-
65
+150
°
C
P tot
power dissipation
T amb =
- 40 to +125 ° C; note 2
-
500
mW
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO14 packages: above 70
C derate linearly with 8 mW/K.
For SSOP14 and TSSOP14 packages: above 60 ° C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
°
°
C derate linearly with 4.5 mW/K.
2003 May 07
5
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