DBL10 - Schematics.pdf

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COMPAL CONFIDENTIAL
MODEL NAME :
DBL10 -- Sapporo X
1
1
COMPAL P/N :
PCB NO :
DA8BL10L000
LA-1931
Revision :
0.2
2
DBL10 -- Sapporo X Schematics Document
2
uFCBGA/uFCPGA NorthWood MT
2003-06-09 0.2 Gerber Out Version
3
3
4
4
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size
Document Number
R e v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401264
0C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate:
¬P
듁ꑔ ꑃꓫ
09, 2003
Sheet
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of
48
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Compal confidential
Block Diagram
Model : DBL10 -- Sapporo X
NorthWood-MT -- 533
Fan Control 1
page 33
Prescott-MT -- 533
+12VALW
Celeron-MT -- 400
Thermal Sensor
+5VALW
Clock Generator
1
1
CPU Bypass
page 6
ADM1032AR
+1.2VP
uFCPGA CPU
478pin
ICS950810CG
+CPU_CORE
+5VS
+3VS
Fan Control 2
page 33
page 4,5
page 5
page 14
+12VALW
+5VALW
HA#(3..31)
System Bus
HD#(0..63)
400/533 MHz
TV Encoder
TV-OUT Signal
by DVOC
Memory
BUS(DDR)
DDR-DIMM X2
TV OUT Connector
page 15
CH7011A
BANK 0, 1, 2, 3
INTEL
+2.5V 200/266/333MHz
+3VS
+3VS
+1.5VS
Montara-GT 852GME
+2.5V
page 15
+2.5V
+1.25VS
CRT Connector
page 16
CRT Signal
page 11,12,13
732 BGA
+5VS
+3VS
+3VS
+CPU_CORE
page 7,8,9,10
LVDS Connector
LVDS Signal
B+
page 16
2
2
HUB LINK 1.5
+1.5VS
66MHz
USB Ports X2
( X1 reserve )
+3VS
+3VALW
+1.5VS
+1.5VALW
+CPU_CORE
VCC5REF
VCC5REFSUS
PCI BUS
+3VS 33MHz
INTEL
48MHz
USB 2.0/1.1
+5V
page 27
IDSEL:AD18
PIRQG#
IDSEL:AD17
PIRQF#
IDSEL:AD20
PIRQA#
IDSEL:AD16
PIRQE#
ICH4-M
AC-LINK
24.576MHz
421 BGA
CardBus
IEEE 1394
LAN
RTL8101L
Minipci CONN
ATA100
MDC
WIRELESS & Dubug
CB1410
VT6301S
page 17,18,19
+5VS
+3V
+3VS
+3V
+2.5VLAN
+3V
+3VS
+3V
+3VS
+3VS
+5VS
page 25
page 23
page 21
page 20
+3V
page 28
LPC BUS
+3VS
33MHz
Cable
PWR Controller & Slot
1394 Conn. page 20
IDE HDD
IDE ODD
AC97 Codec
3
+12VALW +5VALW
+3VALW
3
RJ45
ALC202
RJ11
page 24
page 22
+5VS
+5VCD
+5VALW -> +VDDA
Super I/O
Embedded Controller
page 26
page 26
+3VS
page 28
Cable
SMs FDC47N227
NS PC87591L
SIDE IRQ14
PIDE IRQ15
+3VS
SW Board Conn
+3VS
+3VALW
On/Off BTN &
User Keys page 33
page 30
page 31
EQ
page 29
+5VALW
page 33
+5VCD
RTC Batt.
MIC Phone
page 29
+3VALW
page 33
EC DEBUG & Int. KB
page 31
Parallel
page 30
+5VDDA
+3VALW
+5VS
AMP TPA6011A4
Power Circuit
DC/DC
DC/DC Interface
Suspend
LINE IN
+5VDDA
BIOS & Ext. IO
+5VALW page 29
+3VALW
+5VALW
FIR
page 32
page 36
+5VS
page 30
LID SW & Kill SW
page 33
+3VALW
Debug COM Port
HeadPhone
Touch Pad
page 33
INT. Speaker
4
+5V
page 30
+AUD_VREF
4
+5VS
page 29
page 29
LID Hibernation
page 35
+5VALW
+RTC_VREF
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size
Document Number
R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401264
0C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
,
걐듁ꑔ ꑃꓫ 09, 2003
Sheet
2
of
48
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955693351.592.png 955693351.603.png 955693351.614.png 955693351.625.png 955693351.636.png 955693351.647.png 955693351.658.png 955693351.669.png 955693351.680.png 955693351.691.png 955693351.702.png 955693351.713.png 955693351.724.png 955693351.735.png 955693351.746.png 955693351.758.png 955693351.769.png 955693351.780.png 955693351.791.png 955693351.801.png 955693351.812.png 955693351.823.png 955693351.834.png 955693351.845.png 955693351.856.png 955693351.868.png 955693351.879.png 955693351.890.png 955693351.901.png 955693351.912.png 955693351.923.png 955693351.934.png 955693351.945.png 955693351.956.png 955693351.967.png 955693351.979.png 955693351.990.png 955693351.1001.png 955693351.1012.png 955693351.1023.png 955693351.1034.png 955693351.1045.png 955693351.1056.png 955693351.1067.png 955693351.1078.png 955693351.1090.png 955693351.1101.png 955693351.1112.png 955693351.1123.png 955693351.1134.png 955693351.1145.png 955693351.1156.png 955693351.1167.png 955693351.1178.png 955693351.1189.png 955693351.002.png 955693351.013.png 955693351.024.png 955693351.035.png 955693351.046.png 955693351.057.png 955693351.068.png 955693351.079.png 955693351.090.png 955693351.101.png 955693351.113.png 955693351.124.png 955693351.135.png 955693351.146.png 955693351.157.png 955693351.168.png 955693351.179.png 955693351.190.png 955693351.201.png 955693351.212.png 955693351.224.png 955693351.234.png 955693351.235.png 955693351.236.png 955693351.237.png 955693351.238.png 955693351.239.png 955693351.240.png 955693351.241.png 955693351.242.png 955693351.244.png 955693351.245.png 955693351.246.png 955693351.247.png 955693351.248.png 955693351.249.png 955693351.250.png 955693351.251.png 955693351.252.png 955693351.253.png 955693351.255.png 955693351.256.png 955693351.257.png 955693351.258.png 955693351.259.png 955693351.260.png 955693351.261.png 955693351.262.png
 
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Power Managment table
Voltage Rails
Power Plane
Description
S1
S3
S5
+5VS
Signal
+1.5VALW
+5V
VIN
B+
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
1.2V switched power rail for CPU AGTL Bus
N/A
N/A
N/A
N/A
+3VS
+3VALW
+3V
+2.5V
N/A
N/A
+1.5VS
D
D
+5VALW
+12VALW
+CPU_CORE
+CPU_CORE
ON
OFF
OFF
State
+1.2V
+1.2V
ON
ON
OFF
+1.25VS
+1.25VS
1.25V switched power rail
ON
OFF
OFF
+1.5VALW
1.5V always on power rail
1.5V power rail
1.5V switched power rail
ON
ON
ON
S0
ON
ON
ON
+1.5V
ON
ON
OFF
+1.5VS
ON
OFF
OFF
S1
ON
ON
ON
+2.5V
2.5V power rail
ON
ON
OFF
+3VALW
3.3V always on power rail
ON
ON
ON
S3
ON
ON
OFF
+3V
3.3V power rail
ON
ON
OFF
+3VS
3.3V switched power rail
ON
OFF
OFF
S5 S4/AC
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON
+5V
5V power rail
ON
ON
OFF
S5 S4/AC don't exist
OFF
OFF
OFF
+5VS
5V switched power rail
ON
OFF
OFF
ON
+12VALW
12V always on power rail
ON
ON
C
C
+RTCBATT
RTC power
ON
ON
ON
Board ID Table for AD channel
Vcc
3.3V +/- 5%
100K +/- 5%
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Ra
Board ID
Rb
V
min
V
typ
V AD_BID max
AD_BID
AD_BID
0
1
2
3
0
8.2K +/- 1%
0 V
0.216 V
0 V
0 V
0.250 V
0.289 V
Ext ernal PCI Devices ( follow PCI IRQ routing plannig ver0.2.0 4 )
Device
18K +/- 1%
33K +/- 1%
56K +/- 1%
100K +/- 1%
200K +/- 1%
0.436 V
0.712 V
0.503 V
0.819 V
0.538 V
0.875 V
IDSEL#
REQ#/GNT#
Interrupts - (ICH4-M)
CardBus (ENE-CB1410)
AD20
2
PIRQA#
4
5
6
7
1.036 V
1.453 V
1.185 V
1.264 V
IEEE 1394 (VIA-VT6301S)
AD16
0
PIRQE#
1.650 V
1.759 V
LAN (Realtek-RTL8101L)
AD17
3
P IRQF#
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
Mini-PCI
AD18
1/1
PIRQG#
NC
3.300 V
B
B
Board ID
0
1
2
3
4
5
6
PCB Revision
0.1
EC SM Bus1 address
EC SM Bus2 address
Device
Address
Device
Address
Smart Battery
EEPROM(24C16)
0001 011X b
ADM1032
1001 100X b
1010 000X b
7
ICH4 SM Bus address
A
A
Device
Address
CLK GEN ( ICS-950810)
1101 001X
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size
Document Number
R e v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401264
0C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate:
¬P
듁ꑔ ꑃꓫ
09, 2003
Sheet
3
of
48
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+CPU_CORE
D
D
JCPU1A
HA#[3..31]
HD#[0..63]
<7>
HA#[3..31]
HD#[0..63] <7>
HA#3
HD#0
K2
B21
A#3
D#0
HA#4
HD#1
K4
B22
A#4
D#1
HA#5
HD#2
L6
A23
A#5
D#2
HA#6
POWER
HD#3
K1
A25
A#6
D#3
HA#7
HD#4
L3
C21
A#7
D#4
HA#8
HD#5
M6
D22
A#8
D#5
HA#9
HD#6
L2
B24
A#9
D#6
HA#10
HD#7
M3
C23
A#10
D#7
HA#11
HD#8
M4
C24
A#11
D#8
HA#12
HD#9
N1
B25
A#12
D#9
HA#13
HD#10
M1
G22
A#13
D#10
HA#14
HD#11
N2
H21
A#14
D#11
HA#15
HD#12
N4
C26
A#15
D#12
HA#16
N5
D23
HD#13
A#16
D#13
HA#17
T1
J21
HD#14
A#17
D#14
HA#18
R2
D25
HD#15
A#18
D#15
HA#19
P3
H22
HD#16
A#19
D#16
HOST
ADDR
HA#20
P4
E24
HD#17
A#20
D#17
HA#21
R3
G23
HD#18
A#21
D#18
HA#22
T2
F23
HD#19
A#22
D#19
HA#23
U1
F24
HD#20
A#23
D#20
C
HA#24
P6
E25
HD#21
C
A#24
D#21
HA#25
U3
F26
HD#22
A#25
D#22
HA#26
HD#23
T4
D26
A#26
D#23
HA#27
HD#24
V2
L21
A#27
D#24
HA#28
HD#25
R6
G26
A#28
D#25
HA#29
HD#26
W1
H24
A#29
D#26
HA#30
HD#27
T5
M21
A#30
D#27
HA#31
Northwood-MT
Prescott-MT
HD#28
U4
L22
A#31
D#28
HD#29
V3
J24
A#32
D#29
HOST
ADDR
HD#30
W2
K23
A#33
D#30
HD#31
Y1
H25
A#34
D#31
HD#32
AB1
M23
A#35
D#32
H_REQ#[0..4]
HD#33
N22
<7>
H_REQ#[0..4]
D#33
HD#34
P21
D#34
H_REQ#0
HD#35
J1
M24
REQ#0
D#35
H_REQ#1
HD#36
K5
N23
REQ#1
D#36
H_REQ#2
HD#37
J4
M26
REQ#2
D#37
H_REQ#3
J3
N26
HD#38
REQ#3
D#38
H_REQ#4
H3
N25
HD#39
REQ#4
D#39
H_ADS#
G1
R21
HD#40
<7>
H_ADS#
ADS#
D#40
P24
HD#41
D#41
R25
HD#42
D#42
+CPU_CORE
CONTROL
AC1
R24
HD#43
AP#0
D#43
V5
T26
HD#44
AP#1
D#44
AA3
T25
HD#45
BINIT#
D#45
R15
1
2
56_0402_1%
AC3
T22
HD#46
IERR#
D#46
T23
HD#47
D#47
HD#48
U26
D#48
HD#49
H6
U24
<7>
H_BREQ0#
BR0#
D#49
B
B
HD#50
D2
U23
<7>
H_BPRI#
BPRI#
D#50
HD#51
G2
V25
<7>
H_BNR#
BNR#
D#51
HD#52
G4
U21
<7>
H_LOCK#
LOCK#
D#52
HD#53
V22
D#53
CLK
HD#54
V24
D#54
CLK_CPU_BCLK
HD#55
AF22
W26
<14>
CLK_CPU_BCLK
BCLK0
D#55
CLK_CPU_BCLK#
HD#56
AF23
Y26
<14>
CLK_CPU_BCLK#
BCLK1
D#56
HD#57
W25
D#57
CON
TROL
HD#58
Y23
D#58
HD#59
Y24
D#59
GND
POWER
HD#60
F3
Y21
<7>
H_HIT#
HIT#
D#60
HD#61
E3
AA25
<7>
H_HITM#
HITM#
D#61
HD#62
E2
AA22
<7>
H_DEFER#
DEFER#
D#62
AA24
HD#63
D#63
FOX_PZ47803-274A-42_Prescott
+CPU_CORE
BOOTSEL
2
1
A
BOOTSELECT
<44>
A
R8
@0_0402_5%
R_C
Pop: Northwood
Depop: Prescott
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size
Document Number
R e v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401264
0C
Custom
D ate:
¬P
듁ꑔ ꑃꓫ
09, 2003
Sheet
4
of
48
5
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2
1
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955693351.382.png 955693351.383.png 955693351.385.png 955693351.386.png 955693351.387.png 955693351.388.png 955693351.389.png 955693351.390.png 955693351.391.png 955693351.392.png 955693351.393.png 955693351.394.png 955693351.396.png 955693351.397.png 955693351.398.png 955693351.399.png 955693351.400.png 955693351.401.png 955693351.402.png 955693351.403.png 955693351.404.png 955693351.405.png 955693351.407.png 955693351.408.png 955693351.409.png 955693351.410.png 955693351.411.png 955693351.412.png 955693351.413.png 955693351.414.png 955693351.415.png 955693351.416.png 955693351.418.png 955693351.419.png 955693351.420.png 955693351.421.png 955693351.422.png 955693351.423.png 955693351.424.png 955693351.425.png 955693351.426.png 955693351.427.png 955693351.429.png 955693351.430.png 955693351.431.png 955693351.432.png 955693351.433.png 955693351.434.png 955693351.435.png 955693351.436.png 955693351.437.png 955693351.438.png 955693351.440.png 955693351.441.png 955693351.442.png 955693351.443.png 955693351.444.png 955693351.445.png 955693351.446.png 955693351.447.png 955693351.448.png 955693351.449.png 955693351.451.png 955693351.452.png 955693351.453.png 955693351.454.png 955693351.455.png 955693351.456.png 955693351.457.png 955693351.458.png 955693351.459.png 955693351.460.png 955693351.462.png 955693351.463.png 955693351.464.png 955693351.465.png 955693351.466.png 955693351.467.png 955693351.468.png 955693351.469.png 955693351.470.png 955693351.471.png 955693351.473.png 955693351.474.png 955693351.475.png 955693351.476.png 955693351.477.png 955693351.478.png 955693351.479.png 955693351.480.png 955693351.481.png 955693351.482.png 955693351.484.png 955693351.485.png 955693351.486.png 955693351.487.png 955693351.488.png 955693351.489.png 955693351.490.png 955693351.491.png 955693351.492.png 955693351.493.png 955693351.495.png 955693351.496.png 955693351.497.png 955693351.498.png 955693351.499.png 955693351.500.png 955693351.501.png 955693351.502.png 955693351.503.png 955693351.504.png 955693351.506.png 955693351.507.png 955693351.508.png 955693351.509.png 955693351.510.png 955693351.511.png 955693351.512.png 955693351.513.png 955693351.514.png 955693351.515.png 955693351.517.png 955693351.518.png 955693351.519.png 955693351.520.png 955693351.521.png 955693351.522.png 955693351.523.png 955693351.524.png 955693351.525.png 955693351.526.png 955693351.528.png 955693351.529.png 955693351.530.png 955693351.531.png 955693351.532.png 955693351.533.png 955693351.534.png 955693351.535.png 955693351.536.png 955693351.537.png 955693351.539.png 955693351.540.png 955693351.541.png 955693351.542.png 955693351.543.png 955693351.544.png 955693351.545.png 955693351.546.png 955693351.547.png 955693351.548.png 955693351.550.png 955693351.551.png 955693351.552.png 955693351.553.png 955693351.554.png 955693351.555.png 955693351.556.png 955693351.557.png 955693351.558.png 955693351.559.png 955693351.561.png 955693351.562.png 955693351.563.png 955693351.564.png 955693351.565.png 955693351.566.png 955693351.567.png 955693351.568.png 955693351.569.png 955693351.570.png 955693351.572.png 955693351.573.png 955693351.574.png 955693351.575.png 955693351.576.png 955693351.577.png 955693351.578.png 955693351.579.png 955693351.580.png 955693351.581.png 955693351.582.png 955693351.583.png 955693351.584.png 955693351.585.png 955693351.586.png 955693351.587.png 955693351.588.png 955693351.589.png 955693351.590.png 955693351.591.png 955693351.593.png 955693351.594.png 955693351.595.png 955693351.596.png 955693351.597.png 955693351.598.png 955693351.599.png 955693351.600.png 955693351.601.png 955693351.602.png 955693351.604.png 955693351.605.png 955693351.606.png 955693351.607.png 955693351.608.png 955693351.609.png 955693351.610.png 955693351.611.png 955693351.612.png 955693351.613.png 955693351.615.png 955693351.616.png 955693351.617.png 955693351.618.png 955693351.619.png 955693351.620.png 955693351.621.png 955693351.622.png 955693351.623.png 955693351.624.png 955693351.626.png 955693351.627.png 955693351.628.png 955693351.629.png 955693351.630.png 955693351.631.png 955693351.632.png 955693351.633.png 955693351.634.png 955693351.635.png 955693351.637.png 955693351.638.png 955693351.639.png 955693351.640.png 955693351.641.png 955693351.642.png 955693351.643.png 955693351.644.png 955693351.645.png 955693351.646.png 955693351.648.png 955693351.649.png 955693351.650.png 955693351.651.png 955693351.652.png 955693351.653.png 955693351.654.png 955693351.655.png 955693351.656.png 955693351.657.png 955693351.659.png 955693351.660.png 955693351.661.png 955693351.662.png 955693351.663.png 955693351.664.png 955693351.665.png 955693351.666.png 955693351.667.png 955693351.668.png 955693351.670.png 955693351.671.png 955693351.672.png 955693351.673.png 955693351.674.png 955693351.675.png 955693351.676.png 955693351.677.png 955693351.678.png 955693351.679.png 955693351.681.png 955693351.682.png 955693351.683.png 955693351.684.png 955693351.685.png 955693351.686.png 955693351.687.png 955693351.688.png 955693351.689.png 955693351.690.png 955693351.692.png 955693351.693.png 955693351.694.png 955693351.695.png 955693351.696.png 955693351.697.png 955693351.698.png 955693351.699.png 955693351.700.png 955693351.701.png 955693351.703.png 955693351.704.png 955693351.705.png 955693351.706.png 955693351.707.png 955693351.708.png 955693351.709.png 955693351.710.png 955693351.711.png 955693351.712.png 955693351.714.png 955693351.715.png 955693351.716.png 955693351.717.png 955693351.718.png 955693351.719.png 955693351.720.png 955693351.721.png 955693351.722.png 955693351.723.png 955693351.725.png 955693351.726.png 955693351.727.png 955693351.728.png 955693351.729.png 955693351.730.png 955693351.731.png 955693351.732.png 955693351.733.png 955693351.734.png 955693351.736.png 955693351.737.png 955693351.738.png 955693351.739.png 955693351.740.png 955693351.741.png 955693351.742.png 955693351.743.png 955693351.744.png 955693351.745.png 955693351.747.png 955693351.748.png 955693351.749.png 955693351.750.png 955693351.751.png 955693351.752.png 955693351.753.png 955693351.754.png 955693351.755.png 955693351.756.png 955693351.759.png 955693351.760.png 955693351.761.png 955693351.762.png 955693351.763.png 955693351.764.png 955693351.765.png 955693351.766.png 955693351.767.png 955693351.768.png 955693351.770.png 955693351.771.png 955693351.772.png 955693351.773.png 955693351.774.png 955693351.775.png 955693351.776.png 955693351.777.png 955693351.778.png 955693351.779.png 955693351.781.png 955693351.782.png 955693351.783.png 955693351.784.png 955693351.785.png 955693351.786.png 955693351.787.png 955693351.788.png 955693351.789.png 955693351.790.png 955693351.792.png 955693351.793.png 955693351.794.png 955693351.795.png 955693351.796.png 955693351.797.png 955693351.798.png
 
5
4
3
2
1
GND
H_SKTOCC#
R320
@33_0402_5%
R321
0 _0402 _5 %
H_DPSLPR#
1
2
H_DPSLP#
<8,17>
JCPU1B
H_GHI#
1
2
PM_CPUPERF#
<18>
+CPU_CORE
R55
0_0402_5%
H_RS#[0 . .2]
<7>
H_RS#[0..2]
+H_GTLREF
H_RS#0
F1
J26
RS#0
DP#0
C33
1
2
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
H_RS#1
G5
K25
RS#1
DP#1
GROUND
R49
51_0402_5%
H_RS#2
F4
K26
1
2
D
D
RS#2
DP#2
1
2
AB2
L25
RSP#
DP#3
CON
TROL
R44
51_0402_5%
H_TRDY#
J6
220P_0603_50V8J
<7>
H_TRDY#
TRDY#
1
2
AA21
GTLREF0
R14
51_0402_5%
AA6
GTLREF1
1
2
F20
GTLREF2
REF
R38
51_0402_5%
H_A20M#
R_G
C6
F6
<17>
H_A20M#
A20M#
GTLREF3
H_FERR#
R326
@0_0402_5%
1
2
B6
<17>
H_FERR#
FERR#
+CPU_CORE
R41
51_0402_5%
H_IGNNE#
B2
AE26
1
2
<17>
H_IGNNE#
IGNNE#
OPTIMIZED/COMPAT#
ITP_BPM#5
H_SMI#
1
2
B5
<17>
H_SMI#
SMI#
R13
51_0402_5%
H_PWRGD
AB23
<17>
H_PWRGD
PWRGOOD
H_STPCLK#
Y4
AD24
1
2
<17>
H_STPCLK#
STPCLK#
TESTHI0
R80
56_0402_5%
AA2
TESTHI1
H_PWRGD
H_INTR
LEGACY
1
2
D1
AC21
1
2
<17>
H_INTR
LINT0
TESTHI2
R84
300_0402_5%
H_NMI
R79
56_0402_5%
E5
AC20
<17>
H_NMI
LINT1
TESTHI3
H_INIT#
W5
AC24
<17>
H_INIT#
INIT#
TESTHI4
+CPU_CORE
H_RESET#
AB25
AC23
<7>
H_RESET#
RESET#
TESTHI5
R52
56_0402_5%
AA20
1
2
TESTHI6
ITP
R78
56_0402_5%
AB22
1
2
TESTHI7
H_DBSY#
R37
56_0402_5%
H5
U6
1
2
<7>
H_DBSY#
DBSY#
TESTHI8
H_DRDY#
MISC
R40
56_0402_5%
H2
W4
1
2
<7>
H_DRDY#
DRDY#
TESTHI9
2
1
ITP_TDI
H_BSEL0
AD6
Y3
1
2
R43
56_0402_5%
<14>
H_BSEL0
BSEL0
TESTHI10
R9
150_0402_5%
AD5
A6
H_GHI#
1
2
R57
300_0402_5%
BSEL1
TESTHI11
AD25
H_DPSLPR#
1
2
R322
@56_0402_5%
TESTHI12
2
1
ITP_TMS
THER
MAL
H_DSTBN#[0..3]
R1
39.2_0603_1%
H_THERMDA
B3
Northwood-MT
Prescott-MT
THERMDA
H_DSTBN#[0..3] <7>
H_THERMDC
C4
THERMDC
E22
H_DSTBN#0
DSTBN#0
<18>
H_THERMTRIP#
2
1
ITP_TRST#
H_THERMTRIP#
A2
K22
H_DSTBN#1
THERMTRIP#
DSTBN#1
C
R21
680_0402_5%
R22
H_DSTBN#2
C
DSTBN#2
W22
H_DSTBN#3
DSTBN#3
DATA
H_DSTBP#[0..3]
ITP_BPM#0
AC6
H_DSTBP#[0..3] <7>
BPM#0
ITP_TCK
ITP_BPM#1
2
1
AB5
BPM#1
MISC
R19
27.4_0603_1%
ITP_BPM#2
H_DSTBP#0
AC4
F21
BPM#2
DSTBP#0
ITP_BPM#3
H_DSTBP#1
Y6
J23
BPM#3
DSTBP#1
ITP_BPM#4
H_DSTBP#2
AA5
P23
BPM#4
DSTBP#2
ITP_BPM#5
H_DSTBP#3
AB4
W23
BPM#5
DSTBP#3
H_ADSTB#0
<7>
+IOPLL
+CPU_CORE
H_ADSTB#1
<7>
0_0603_5%
1
ITP_TCK
ADDR
H_ADSTB#0
D4
L5
TCK
ADSTB#0
R325
ITP_TDI
ITP
H_ADSTB#1
2
C1
R5
TDI
ADSTB#1
+1.2V
H_DBI#[0..3]
D5
TDO
H_DBI#[0..3] <7>
@0_0805_5%
1
ITP_TMS
F7
TMS
R324
ITP_TRST#
H_DBI#0
2
E6
E21
TRST#
DBI#0
L26
LQG21F4R7N00_0805
H_DBI#1
G25
DBI#1
VCCIOPLL
DATA
H_DBI#2
1
2
AD20
P26
VCCIOPLL
DBI#2
VCCA
AE23
V21
H_DBI#3
VCCA
DBI#3
MISC
1
2
2
1
+3VALW
LQG21F4R7N00_0805
VCCSENSE
A5
AE25
R323
150_0402_5%
1
1
<44>
VCCSENSE
VCCSENSE
DBR#
L27
VSSSENSE
A4
1
2
<44>
VSSSENSE
VSSSENSE
+CPU_CORE
+
+
AF3
R10
100K_0402_1%
+1.2V
VCCVIDLB
MISC
C331
@33U_D2_16VM
C332
33U_D2_16VM
C3
H_PROCHOT#
H_PROCHOT#
<43>
PROCHOT#
AD22
V6
2
2
VSSA
MCERR#
ITP
CLK
VSSA
AB26
H_SLP#
H_SLP#
<17>
SLP#
AC26
A22
<14>
CLK_CPU_ITP
ITP_CLK0
NC1
GROUND
MISC
AD26
A7
<14>
CLK_CPU_ITP#
ITP_CLK1
NC2
AF25
NC3
B
B
L24
AF24
COMP0
NC4
1
2
P1
AE21
COMP1
NC5
R82
61.9_0603_1%
GTL Reference Voltage
Layout note :
1
2
R20
61.9_0603_1%
1. Place R_A and R_B near CPU (Within 1.5").
Comp0/1 need keep 25
mils trace width
+1.2V
+CPU_CORE
FOX_PZ47803-274A-42_Prescott
1
C276
0.1U_0402_16V7K
+3VS
Pop: Prescott
Depop: Northwood
R56
51.1_0603_1%
2
+3VS
R270
1
2
1K_0402_5%
CPU Temperature Sensor
R271
1
2
1K_0402_5%
R12
@2.43K_0603_1%
1
R272
1
2
1K_0402_5%
R61
R267
1
2
1K_0402_5%
2
+1.2V
+H_GTLREF
1
2
R266
1
2
1K_0402_5%
R16
1
2
1K_0402_5%
1
200_0402_5%
1
R59
86.6_0603_1%
C34
1U_0603_6.3V6M
H_VID_PW RGD
<35>
H_THERMDA
C27
1U_0402_6.3V4Z
<44>
CPU_VID[0..5]
2
R48
10K_0402_5%
2
1
U6
C24
2200P_0603_50V7K
A
A
2
1
2
D+
VDD1
H_THERMDC
3
6
D-
ALERT#
8
4
<32>
EC_SMC2
SCLK
THERM#
Compal Electronics, Inc.
7
5
<32>
EC_SMD2
SDATA
GND
Title
SCHEMATIC, M/B LA-1931
ADM1032ARM_RM8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size
Document Number
R e v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401264
0C
Custom
D ate:
¬P
듁ꑔ ꑃꓫ
09, 2003
Sheet
5
of
48
5
4
3
2
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