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Power Management
Texas Instruments Incorporated
Using the UCC3580-1 controller for highly
efficient 3.3-V/100-W isolated supply design
By Brian M. King (Email: b-king1@ti.com)
Advanced Analog Products
Power-supply modules offer an attractive solution for
providing the bulk power conversion in telecom systems.
Modules offer a ready-made solution in a single package
but can be quite expensive. The alternative, of course, is
to build a power supply from discrete components. A dis-
crete design can dramatically reduce production costs but
requires a more intense engineering effort. For those willing
to invest the effort, Figures 1 and 2 present a discrete
solution that provides up to 100 W at 3.3 V from an isolated
48-V input. This design matches or exceeds the perform-
ance, consumes less board area, and costs significantly
less than many half-brick modules that have the same
power requirements.
This design uses a UCC3580-1 to control an active-
clamp forward converter with self-driven synchronous
rectifiers. The topology allows the circuit to achieve effi-
ciencies of up to 93%. Additional features included in the
design are remote sense connections for point-of-load
regulation, input undervoltage, input overvoltage, output
overvoltage, and overcurrent protection.
Circuit description
Both an n-channel FET (Q1) and a p-channel FET (Q2)
drive the 6-turn, primary winding of the active-clamp
transformer. The UCC3580-1 controller provides the drive
for both MOSFETs. The n-channel drive is provided
straight from the UCC3580-1, while the p-channel drive is
inverted through the circuit of C7, D9, and R100. Figure 3
shows the drain-source waveforms of the primary and sec-
ondary MOSFETs.
While Q1 is on, power is delivered to the secondary, and
magnetizing energy is being stored in the transformer.
During this time, Q2 is off, and the clamp capacitor (C2) is
out of the circuit and remains charged at a constant voltage
level. When Q1 turns off, the leakage and magnetizing
currents charge up the drain-to-source capacitance of Q1.
Once the drain-to-source voltage of Q1 exceeds the voltage
across the clamp capacitor, the body diode of Q2 begins to
conduct. With the body diode of Q2 conducting, the mag-
netizing current now begins to charge the clamp capacitor.
Some time after the body diode of Q2 has begun to
conduct, the controller turns on Q2. This provides zero-
current switching for Q2. The clamp capacitor continues
to charge until the magnetizing current is reduced to 0 A.
At this point, the magnetizing current reverses, and the
clamp capacitor begins to discharge until the controller
turns off the p-channel FET. After Q2 turns off, the clamp
capacitor remains at a fixed voltage. There is a fixed delay
before Q1 turns on. During this delay, the energy in the
parasitic components discharges the V DS of Q1 towards
Figure 1. Power stage schematic
C106
4700 pF
2kV
L1
PA0373
BIAS
V
= 3.3 V @ 30 A
R12
OUT
1 1
Q5, Q6, Q8, Q9 = HAT2099H
Q3
FZT655
V OUT+
49.9 k Ω
D2
D3
12 V
C11
180 µF
6.3 V
C12
180 µF
6.3 V
C1
180 µF
6.3 V
C102
10 µF
6.3 V
+
+
+
C8
10 µF
6
7
MMSD914
T1
PA0369
35-V to
75-V Input
Q8
Q9
2
9
V IN+
V OUT–
Q5
Q6
C22
1µF
100 V
C23
1µF
100 V
C24
1µF
100 V
6T
1T
4
8
C2 0.1 µF
200 V
Q1
Si7846DP
D100
BAT54
8765
4
N_DRV
R101
1k Ω
Q2
IRF6217
R103
0.1
1W
R2
0.1
1W
I_SNS
Q100
MMBT3904
3
2
1
C100
1µF
V IN–
D101
5.1 V
BIAS2
P_DRV
C101
10 µF
SENSE–
8
Analog Applications Journal
Analog and Mixed-Signal Products
4Q 2002
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Texas Instruments Incorporated
Power Management
Figure 2. Control stage schematic
R16
34.8 k Ω
R102
10 Ω
R3
1k Ω
I_SNS
V OUT+
C6
0.1 µF
BIAS2
U1
UCC2580D-1
U7
H11A817B
R4
200 k Ω
C16
100 pF
C104
1µF
R28
499 Ω
R20
10 Ω
C5
0.1 µF
SHDN
DELAY
1
16
4
1
LINE
SS
2
15
SENSE+
BIAS
VDD
REF
REF
R24
23.7
k Ω
R23
750
Ω
3
14
3
2
N_DRV
EAIN
OUT1
C9
0.1 µF
4
13
C15
33 pF
R22
49.9 k Ω
PGND
EAOUT
5
12
C14
3300
pF
C13
1000
pF
R25
10 k Ω
R26
10 k Ω
OUT2
OSC1
6
11
R27
1k Ω
C7
1µF
16 V
CLK
OSC2
7
10
C103
100 pF
C19
1000 pF
GND
RAMP
8
9
R5
4.02
k Ω
P_DRV
R7
100 k Ω
R6
45.3 k Ω
U2
TLV431A
R37
30.1 k Ω
D9
BAT54
R100
10 k Ω
V IN+
SENSE–
C4
330 pF
C3
100 pF
R8
150 k Ω
BIAS2
C105
1µF
R19
10 Ω
BIAS
U5
H11A817B
R38
10 k Ω
V IN+
V OUT+
C17
0.1 µF
R32
150
k Ω
4
1
R30 10 k Ω
Q4
MMBT3904
R33
10 k Ω
ON/OFF
1
3
2
5
R9
26.7 k Ω
R29
3.48 k Ω
R35
499 Ω
U4
TL331DBV
4
R31
9.53 k Ω
3
U6
TLV431A
C18
100 pF
R21
100 k Ω
R34
4.53 k Ω
2
REF
SENSE–
R41
4.99 k Ω
BAS16
D4
V IN . This allows softer turn-on and reduces switching
losses in Q1 (see Figure 4).
The secondary power stage consists of the synchronous
rectifiers (Q5, Q6, Q8, and Q9) and the output filter (L1,
C1, C11, C12, and C102). When Q1 is on, the voltage on
the secondary of T1 ensures that both Q8 and Q9 are on,
while Q5 and Q6 are off. During this time, a voltage equal
to the input voltage divided by the turns ratio of the
transformer is applied across the gate-to-source of Q8 and
Q9, and also across the drain-to-source of Q5 and Q6. Also
during this time, the gate-to-source voltage of Q5 and Q6
is essentially 0 V and is equal to the inductor current
times the r ds(on) of Q8 and Q9.
When Q2 is off, the voltage on the secondary of T1
reverses, and ensures that both Q5 and Q6 are on, while
Q8 and Q9 are off. During this time, the magnitude of the
Figure 3. Power MOSFET drain waveforms
Figure 4. Turn-on of primary-side
n-channel MOSFET
Q1: 50 V/div
V
: 50 V/div
DS
Q2: 50 V/div
Q5 & Q6: 10 V/div
V
: 5 V/div
GS
Q8 & Q9: 10 V/div
Time Scale: 1 µs/div
Time Scale: 100 ns/div
9
Analog Applications Journal
4Q 2002
Analog and Mixed-Signal Products
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Power Management
Texas Instruments Incorporated
transformer secondary voltage is equal to the clamp
capacitor voltage minus the input voltage, divided by
the transformer turns ratio. The peak clamp capaci-
tor voltage will determine the maximum voltage
stress across the gate-to-source of Q5 and Q6, and
also across the drain-to-source of Q8 and Q9. During
this time, the gate-to-source voltage of Q8 and Q9 is
essentially 0 V and is equal to the inductor current
times the r ds(on) of Q5 and Q6.
Two bias voltages are used in this active-clamp
design, one for the primary side and one for the
secondary side. The circuit composed of C8, D2, D3,
L1, Q3, and R12 produces the primary-side bias. D2,
R12, and Q3 form a linear regulator, which is func-
tional only during startup, or during a fault condition.
L1 contains an auxiliary winding that is used to
produce the primary-side bias during normal opera-
tion. The main winding of L1 has 4 turns, while the
auxiliary winding has 16 turns. The auxiliary winding
charges C8 to a voltage equal to the output voltage
times the 16:4 turns ratio of the inductor, minus the diode
drop of D3.
The circuit composed of C100, C101, D100, D101, Q100,
and R101 produces the secondary-side bias. This bias is
required to drive the feedback optocoupler (U7) and the
TLV431 (U2). D100 and C100 peak detect the transformer
secondary voltage. R101, D101, and Q100 form a linear
regulator. The linear regulator is necessary to ensure that
the bias voltage is independent of the input voltage.
Without the linear regulator circuit, a second feedback
loop is introduced into the compensation circuit, which
complicates the compensation design.
Breaking the feedback path with R19 and R20 provides
remote sensing. By connecting the remote sense terminals
directly to the desired regulation point, the converter
compensates for any voltage drops between the output of
the supply and the load. The remote sense terminals must
always be connected to the converter output and output
return. If remote sensing is not required, R19 and R20
may be shorted, in which case regulation will be provided
directly at the converter output filter.
Figure 5. Line and load regulation
3.306
3.304
V
= 36 V
IN
3.302
V
= 48 V
IN
3.3
V
= 72 V
3.298
IN
3.296
0
5
10
15
20
25
30
Load Current (A)
The feedback network is typical of most isolated forward
converters. The TLV431 (U2) incorporates a voltage refer-
ence and transconductance error amplifier into one package.
Providing type III compensation around U2 compensates
the voltage-mode converter. The current transfer ratio of
U7 and the values of R27 and R28 determine the gain of
the optocoupler circuit. The error amplifier of the
UCC3580-1 is used in an inverting configuration, with a
gain of 1 V/V.
The shutdown pin of the UCC3580-1 provides overcurrent
protection. The current is sensed at the source of Q1 by
resistors R2 and R103. Resistor R16 lowers the shutdown
threshold voltage, which improves the converter’s efficiency
by decreasing the required resistance of R2 and R103.
The UCC3580-1 and resistors R8 and R9 control the input
undervoltage protection. The comparator circuit of U4 con-
trols input overvoltage protection. Both input overvoltage
and input undervoltage circuits provide hysteresis. The
circuit of U5 and U6 provides output overvoltage protec-
tion. When the input to U6 exceeds the TLV431 reference
voltage, the converter shuts downs until the overvoltage
condition is gone, at which point a normal soft-start cycle
is initiated.
Performance
The circuit operates from input voltages between
36 and 75 V and at load currents of up to 30 A. The
output voltage typically varies by only 4 mV (0.1%)
over the entire line and load range (see Figure 5).
Most power modules with similar power require-
ments list line and load regulations below 0.2%. The
output ripple voltage of this design is kept below 26
mV (0.8%) over line and load, as shown in Figure 6.
Power modules offer similar ripple performance.
Figure 6. Output ripple voltage
30
25
V
= 72 V
IN
20
15
V
= 36 V
IN
10
V
= 48 V
IN
5
0
0
5
10
15
20
25
30
Load Current (A)
10
Analog Applications Journal
Analog and Mixed-Signal Products
4Q 2002
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Texas Instruments Incorporated
Power Management
Figure 7 compares the efficiency of this design to
the efficiency of modules from two leading module
manufacturers. The data are given for a 48-V input
and 25°C ambient temperature. Module A is typical
of the majority of 3.3-V, half-brick, 100-W modules.
Module B is an example of one of the few modules
that list efficiency at greater than 90%. The discrete
design competes very well with even the most effi-
cient power-supply modules. The efficiency peaks
at 93% at around 12 A and drops to 89% at full-
rated load.
The efficiency, package, and thermal environment
all conspire to limit the maximum load current for an
application. While power modules may be rated for
30 A of load current, the current may actually be
limited to a fraction of this by the internal device
junction temperatures. The same is true of the
discrete design. Modules have an advantage in this
arena because they often are constructed with mate-
rials that provide good heat-sinking properties. With
a discrete design, however, the designer has the opportu-
nity to lay out the circuit board to accommodate for the
power dissipation of hot components. Even with an excel-
lent layout, at these power levels, both the modules and
discrete solution typically require some forced air flow to
achieve the maximum rated current.
To compare the thermal performance of the discrete
design to that of the power modules, the circuit was con-
structed on a 2-oz. copper, 4-layer PCB in a half-brick
footprint (2.3″ x 2.2″). The safe-operating-area (SOA)
curves of the modules and the discrete design are shown
in Figure 8 for a 48-V input and 300 linear feet per minute
(lfm) of air flow. The good heat sinking and high efficiency
of Module B allow it to operate at higher currents than
both Module A and the discrete design. However, even the
good heat sinking of Module A cannot make up for its low
efficiency. Incorporating the discrete design into a larger
PCB allows more copper to be tied to the hot components
(the power MOSFETs) to provide a wider SOA.
Figure 7. Comparison of typical efficiencies
94
92
90
Module B
Discrete Solution
88
86
84
82
Module A
80
78
76
74
5
10
15
20
25
30
Load Current (A)
Conclusion
The decision whether to build a discrete power supply or to
buy premanufactured modules involves trade-offs involving
cost, schedule, and risk. Designing a power supply based
on a reference design, such as the one presented here,
significantly lowers the risk associated with the discrete
approach. In situations where schedule is key, modules are
the logical choice. However, migrating to a discrete power
supply yields significant cost savings, particularly in high-
volume applications.
Related Web sites
analog.ti.com
www.ti.com/sc/device/ partnumber
Replace partnumber with TL331, TLV431A, UCC2580-1
Figure 8. Comparison of SOA curves
95
Module B
85
Discrete
Solution
75
65
55
Module A
45
35
25
0
5
10
15
20
25
30
Load Current (A)
11
Analog Applications Journal
4Q 2002
Analog and Mixed-Signal Products
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