mega103.pdf

Features

• Utilizes the AVR ® RISC Architecture

• AVR – High-performance and Low-power RISC Architecture

– 121 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General-purpose Working Registers + Peripheral Control Registers

– Up to 6 MIPS Throughput at 6 MHz

• Data and Nonvolatile Program Memory

– 128K Bytes of In-System Programmable Flash

Endurance: 1,000 Write/Erase Cycles

– 4K Bytes Internal SRAM

– 4K Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– Programming Lock for Flash Program and EEPROM Data Security

– SPI Interface for In-System Programming

• Peripheral Features

– On-chip Analog Comparator

– Programmable Watchdog Timer with On-chip Oscillator

– Programmable Serial UART

– Master/Slave SPI Serial Interface

– Real-time Counter (RTC) with Separate Oscillator

– Two 8-bit Timer/Counters with Separate Prescaler and PWM

– Expanded 16-bit Timer/Counter System with Separate Prescaler, Compare,

Capture Modes and Dual 8-, 9-, or 10-bit PWM

– Programmable Watchdog Timer with On-chip Oscillator

– 8-channel, 10-bit ADC

• Special Microcontroller Features

– Low-power Idle, Power-save and Power-down Modes

– Software Selectable Clock Frequency

– External and Internal Interrupt Sources

• Specifications

– Low-power, High-speed CMOS Process Technology

– Fully Static Operation

• Power Consumption at 4 MHz, 3V, 25 ° C

– Active: 5.5 mA

– Idle Mode: 1.6 mA

– Power-down Mode: < 1 µA

• I/O and Packages

– 32 Programmable I/O Lines, 8 Output Lines, 8 Input Lines

– 64-lead TQFP

• Operating Voltages

– 2.7 - 3.6V for ATmega103L

– 4.0 - 5.5V for ATmega103

• Speed Grades

– 0 - 4 MHz for ATmega103L

– 0 - 6 MHz for ATmega103

8-bit

Microcontroller

with 128K Bytes

In-System

Programmable

Flash

ATmega103(L)

Rev. 0945G–09/01

Pin Configuration

TQFP

(AD2) PA2

PD7 (T2)

(AD1) PA1

PD6 (T1)

(AD0) PA0

PD5

PD4 (IC1)

PD3 (INT3)

PD2 (INT2)

PD1 (INT1)

PD0 (INT0)

VCC

GND

(ADC7) PF7

(ADC6) PF6

(ADC5) PF5

(ADC4) PF4

XTAL1

XTAL2

(ADC3) PF3

(ADC2) PF2

GND

VCC

(ADC1) PF1

(ADC0) PF0

RESET

AREF

AGND

AVCC

TOSC1

664

INDEX CORNER

TOSC2

PB7 (OC2/PWM2)

ATmega103(L)

0945G–09/01

ATmega103(L)

Description

The ATmega103(L) is a low-power, CMOS, 8-bit microcontroller based on the AVR

RISC architecture. By executing powerful instructions in a single clock cycle, the

ATmega103(L) achieves throughputs approaching 1 MIPS per MHz, allowing the sys-

tem designer to optimize power consumption versus processing speed.

The AVR core is based on an enhanced RISC architecture that combines a rich instruc-

tion set with 32 general-purpose working registers. All the 32 registers are directly

connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be

accessed in one single instruction executed in one clock cycle. The resulting architec-

ture is more code efficient while achieving throughputs up to ten times faster than

conventional CISC microcontrollers.

The ATmega103(L) provides the following features: 128K bytes of In-System Program-

mable Flash, 4K bytes EEPROM, 4K bytes SRAM, 32 general-purpose I/O lines, 8 input

lines, 8 output lines, 32 general-purpose working registers, real-time counter (RTC), 4

flexible timer/counters with compare modes and PWM, UART, programmable watchdog

timer with internal oscillator, an SPI serial port and 3 software-selectable power saving

modes. The Idle mode stops the CPU while allowing the SRAM, timer/counters, SPI port

and interrupt system to continue functioning. The Power-down mode saves the register

contents but freezes the oscillator, disabling all other chip functions until the next inter-

rupt or hardware reset. In Power-save mode, the timer oscillator continues to run,

allowing the user to maintain a timer base while the rest of the device is sleeping.

The device is manufactured using Atmel’s high-density nonvolatile memory technology.

The On-chip ISP Flash allows the program memory to be reprogrammed in-system

through a serial interface or by a conventional nonvolatile memory programmer. By

combining an 8-bit RISC CPU with a large array of ISP Flash on a monolithic chip, the

Atmel ATmega103(L) is a powerful microcontroller that provides a highly flexible and

cost-effective solution to many embedded control applications.

The ATmega103(L) AVR is supported with a full suite of program and system develop-

ment tools including: C compilers, macro assemblers, program debugger/simulators, in-

circuit emulators and evaluation kits.

0945G–09/01

Block Diagram

Figure 1. The ATmega103(L) Block Diagram

PF0 - PF7

PA0 - PA7

PC0 - PC7

VCC

GND

PORTF BUFFERS

PORTA DRIVER/BUFFERS

PORTC DRIVERS

AVCC

ANALOG MUX

ADC

DATA REGISTER

PORTA

DATA DIR.

REG. PORTA

DATA REGISTER

PORTC

8-BIT DATA BUS

AGND

XTAL1

AREF

INTERNAL

OSCILLATOR

XTAL1

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

OSCILLATOR

TOSC2

PROGRAM

FLASH

SRAM

MCU CONTROL

TIMING AND

CONTROL

TOSC1

RESET

INSTRUCTION

GENERAL

PURPOSE

REGISTERS

TIMER/

COUNTERS

ALE

INSTRUCTION

DECODER

INTERRUPT

UNIT

CONTROL

LINES

ALU

EEPROM

STATUS

PROGRAMMING

LOGIC

PEN

SPI

UART

DATA REGISTER

PORTE

DATA DIR.

REG. PORTE

DATA REGISTER

PORTB

DATA DIR.

REG. PORTB

DATA REGISTER

PORTD

DATA DIR.

REG. PORTD

PORTE DRIVER/BUFFERS

PORTB DRIVER/BUFFERS

PORTD DRIVER/BUFFERS

VCC

GND

PE0 - PE7

PB0 - PB7

PD0 - PD7

ATmega103(L)

0945G–09/01

ATmega103(L)

Pin Descriptions

VCC

Supply voltage.

GND

Ground.

Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors

(selected for each bit). The Port A output buffers can sink 20 mA and can drive LED dis-

plays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low,

they will source current if the internal pull-up resistors are activated.

Port A serves as Multiplexed Address/Data bus when using external SRAM.

The Port A pins are tri-stated when a reset condition becomes active, even if the clock is

not running.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output

buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source

current if the pull-up resistors are activated.

Port B also serves the functions of various special features.

The Port B pins are tri-stated when a reset condition becomes active, even if the clock is

not running.

Port C (PC7..PC0)

Port C is an 8-bit output port. The Port C output buffers can sink 20 mA.

Port C also serves as Address output when using external SRAM.

Since Port C is an output only port, the Port C pins are not tri-stated when a reset condi-

tion becomes active.

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output

buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source

current if the pull-up resistors are activated.

Port D also serves the functions of various special features.

The Port D pins are tri-stated when a reset condition becomes active, even if the clock is

not running.

Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port E output

buffers can sink 20 mA. As inputs, Port E pins that are externally pulled low will source

current if the pull-up resistors are activated.

Port E also serves the functions of various special features.

The Port E pins are tri-stated when a reset condition becomes active, even if the clock is

not running

Port F (PF7..PF0)

Port F is an 8-bit input port. Port F also serves as the analog inputs for the ADC.

RESET

Reset input. An external reset is generated by a low level on the RESET pin. Reset

pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter

pulses are not guaranteed to generate a reset.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

0945G–09/01

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