Rahul_Chapter2_PWM.pdf

Chapter 2

2 Space Phasor Based PWM Technique for Multi-level Inverters

Using Only the Instantaneous Amplitudes of Reference Phase

Voltages

2.1 Introduction

The two most widely used PWM schemes for multi-level inverters are the carrier

based sine-triangle PWM (SPWM) techniques and the Space Vector based PWM (SVPWM)

techniques. These modulation techniques are extensively studied for two-level inverters and

their principle are presented in Appendix-I. A brief survey of these schemes is presented in

chapter 1. The SPWM schemes are more simple and easy to implement, whereas the

SVPWM scheme has extended linear range (15 percent more) and better harmonic

performance [46]-[51],[53]. But the conventional SVPWM scheme requires sector

identification and look-up tables for determining the timings for various switching vectors of

the inverter, in all the sectors. This makes the implementation of the SVPWM scheme quite

complicated. A SVPWM scheme, extending the modulation range into over-modulation

range, involves extensive offline computations and look-up tables, to determine the modified

reference vector, in the over-modulation range, extending up to six-step operation [95],[99].

It has been shown for two-level inverters, that a SVPWM like performance can be obtained

with SPWM scheme by adding a common mode voltage of suitable magnitude, to the

sinusoidal reference phase voltage [47],[51].

The SPWM technique, when applied to multi-level inverters uses a number of level

shifted carrier waves for comparing with the reference phase voltage signals [59]. The

2-1

SVPWM for multi-level inverters, presented in [21], involves mapping of the outer sectors to

an inner sub-hexagon sector, for determining the switching time durations, for various

inverter vectors. Then the inverter switching vectors corresponding to the actual sector are

switched, for the time durations, calculated from the mapped inner sectors. It is obvious that

such a scheme, in multi-level inverters, will be very complex, as large number of sectors and

inverter vectors are involved. This will also increase the computation time considerably.

A modulation scheme is presented in [26], where a fixed common mode voltage, is

added to the reference phase voltage throughout the modulation range. It has been shown in

[78] that this common mode addition will not result in the SVPWM like performance, as it

will not center middle inverter vectors, in a switching interval. The common mode voltage to

be added in the reference phase voltages, to achieve SVPWM like performance, is a function

of the modulation index, for multilevel inverters [78]. A SVPWM scheme based on above

principle has been presented in [79], where the switching time for inverter legs are directly

determined from instantaneous phase voltage amplitudes. This technique reduces the

computation time considerably than the conventional SVPWM techniques, but it involves

region identifications based on modulation indices. While this SVPWM scheme works well

for a three-level PWM generation, it cannot be extended to multi-level inverters of higher

levels (more than three), as the region identification becomes more complicated. In the

reference [79], the PWM scheme is presented only for the linear modulation range, and its

extension to over-modulation region remains unaddressed.

The objective of this chapter is to present a generalized SVPWM scheme, for the

entire range of modulation indices including over-modulation, which determines the

switching, times for inverter legs directly from the instantaneous sampled amplitudes of the

reference phase voltages. The proposed SVPWM technique does not involve the checks for

region identification, when compared to the SVPWM scheme presented in [79]. Also, the

algorithm does not require any sector identification and look-up tables, for switching vector

2-2

determination. Thus the scheme is computationally efficient when compared to the

conventional SVPWM schemes, and making it superior for real time implementation. The

proposed SVPWM algorithm can be easily extended to any multi-level inverter

configurations. For experimental verification of the proposed SVPWM scheme, a five-level

inverter structure with open-end winding induction motor is used [26].

2.2 Proposed SVPWM in linear modulation range

In SPWM scheme for two-level inverters, each reference phase voltage is compared with

the triangular carrier and the individual pole voltages are generated, independent of each

other (Appendix-I) [55]. In order to get the maximum possible peak amplitude of

fundamental phase voltage, in linear modulation, a common mode voltage ‘

offset

’ is added to

the reference phase voltages [26],[51], where the magnitude of

offset

(as given by equation

I.7) is equal to,

offset

max

min /2

(2.1)

In (2.1)

max

is the maximum amplitude, among the three sampled reference phase

voltages, while

min

is the minimum amplitude among the three sampled reference phase

voltages, in a sampling interval. The addition of common mode voltage

offset

, results in

centering of the active inverter switching vectors in a sampling interval, making the SPWM

technique equivalent to SVPWM [46]. The equation (2.1) is based on the fact that, in a

sampling interval, the reference phase, which has lowest magnitude, (referred as min-phase )

crosses triangular carrier first, and causes the first transition in the inverter switching state.

While the reference phase, which has the maximum magnitude (now referred as max-phase ),

crosses the carrier last and causes the last switching transition in the inverter switching states,

in a two-level SVPWM scheme (Appendix-I) [51], [78]. Thus the time for switching periods

of active vectors can be determined from the ( max-phase and min-phase ) sampled reference

phase voltage amplitudes, in a two-level inverter scheme [55]. The SPWM technique, for

2-3

multi-level inverters, involves comparison of reference phase voltage signals, with a number

of symmetrical level shifted carrier waves, for PWM generation [59]. It has been shown that

for an n -level inverter, n- 1 level shifted carrier waves are required to compare with sinusoidal

references [59]. Because of the level shifted multi-carriers (Fig. 2.1) the first crossing

(referred as first-cross ) of the reference phase voltage may not be always the min-phase .

Similarly, the last crossing (referred as third-cross ) of the reference phase voltage may not be

always the max-phase .

Fig. 2.1: Modified reference voltages and triangular carriers for a five-level PWM scheme

Thus the offset voltage computation, based on (2.1), is not sufficient to center the middle

inverter switching vectors, in a multi-level PWM scheme, during a sampling period T (Fig.

2.2). In this chapter, a simple technique to determine the offset voltage (to be added to the

reference phase voltage for PWM generation for the entire modulation range) is presented,

based only on the instantaneous amplitudes of reference phase voltages. The idea behind the

proposed scheme is to determine the sampled reference phase, out of the three sampled

reference phases, which crosses the triangular first ( first-cross ) and the reference phase which

crosses the triangular carrier last ( third-cross ). Once the first-cross phase and third-cross

2-4

phase are identified, the principles of offset calculation of (2.1), for the two-level inverter,

can be easily adapted for multilevel SVPWM generation scheme.

Fig. 2.2: The inverter switching vectors and their switching time durations during sampling interval T S

(Reference voltages are within the inner carrier region, M < 0.433)

The SVPWM technique proposed in this chapter presents a novel way to determine the time

instants at which the three reference phases cross the triangular carriers. These time instants

are sorted to find the offset voltage to be added to the reference phase voltages for SVPWM

signal generation for multi-level inverters, for the entire linear modulation range, so that the

middle inverter switching vectors are always centered, (during a switching interval), as in the

case of conventional SVPWM scheme.

2.2.1 Determination of the offset voltage to generate the inverter leg switching times for a

five-level inverter

Fig. 2.1 shows the reference voltage and four triangular carriers used for PWM generation

for a five-level inverter. The modified reference phase voltages are given by,

1 ,

XAB

(2.2)

offset

2-5

, C

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