LMC835.PDF

February 1995

LMC835 Digital Controlled Graphic Equalizer

General Description

The LMC835 is a monolithic, digitally-controlled graphic

equalizer CMOS LSI for Hi-Fi audio. The LMC835 consists

of a Logic section and a Signal Path section made of analog

switches and thin-film silicon-chromium resistor networks.

The LMC835 is used with external resonator circuits to

make a stereo equalizer with seven bands, g 12 dB or g 6

dB gain range and 25 steps each. Only three digital inputs

are needed to control the equalization. The LMC835 makes

it easy to build a m P-controlled equalizer.

The signal path is designed for very low noise and distor-

tion, resulting in very high performance, compatible with

PCM audio.

Features

Y No volume controls required

Y Three-wire interface

Y 14 bands, 25 steps each

Y g 12 dB or g 6 dB gain ranges

Y Low noise and distortion

Y TTL, CMOS logic compatible

Applications

Y Hi-Fi equalizer

Y Receiver

Y Car stereo

Y Musical instrument

Y Tape equalization

Y Mixer

Y Volume controller

Connection Diagrams

Dual-In-Line Package

Molded Chip Carrier Package

TL/H/6753±26

Top View

Order Number LMC835V

See NS Package V28A

TL/H/6753±1

Top View

Order Number LMC835N

See NS Package N28B

C 1995 National Semiconductor Corporation

TL/H/6753

RRD-B30M75/Printed in U. S. A.

Block Diagram

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage, V DD b V SS 18V

Allowable Input Voltage (Note 1) V SS b 0.3V

to V DD a 0.3V

Storage Temperature, T stg b 60 § Cto a 150 § C

Lead Temperature (Soldering, 10 sec), N Pkg a 260 § C

Lead Temperature, V Pkg

Vapor Phase (60 sec)

Operating Ratings

Supply Voltage, V DD b V SS

5V to 16V

Digital Ground (Pin 13)

V SS to V DD

Digital Input (Pins 14, 15, 16)

V SS to V DD

Analog Input (Pins 1, 2, 3, 4, 25, 26, 27)

(Note 1)

V SS to V DD

Operating Temperature, T opr

b 40 § Cto a 85 § C

a 215 § C

Infrared (15 sec)

a 220 § C

Electrical Characteristics (Note 2) V DD e 7.5V, V SS eb 7.5V, A.GND e 0V

LOGIC SECTION

Tested Design

Unit

Symbol

Parameter

Test Conditions

Typ

Limit

(Limit)

(Note 3)

(Note 4)

I DDL

Supply Current

Pins 14, 15, 16 are 0V

0.01

0.5

0.5 mA (Max)

I SSL

Pins 14, 15, 16 are 0V

0.01

0.5

0.5 mA (Max)

I DDH

Pins 14, 15, 16 are 5V

1.3

5 mA (Max)

I SSH

Pins 14, 15, 16 are 5V

0.9

5 mA (Max)

V IH

High-Level Input Voltage

@ Pins 14, 15, 16

1.8

2.3

2.5

V (Min)

V IL

Low-Level Input Voltage

@ Pins 14, 15, 16

0.9

0.6

0.4

V (Max)

f o

Clock Frequency

@ Pin 14

2000

500

kHz (Max)

t w(STB) Width of STB Input

SeeFigure1

0.25

m s (Min)

t setup Data Setup Time

SeeFigure1

0.25

m s (Min)

t hold Data Hold Time

SeeFigure1

0.25

m s (Min)

t cs

De lay f rom Rising Edge of CLOCK SeeFigure1

0.25

m s (Min)

to STB

I IN

Input Current

@ Pins 14, 15, 16 0V k V IN k 5V g 0.01 g 1

m A (Max)

C IN

Input Capacitance

@ Pins 14, 15, 16 f e 1 MHz

Note 1: Pins 2, 3 and 26 have a maximum input voltage range of g 22V for the typical application shown in Figure7.

Note 2: Bold numbers apply at temperature extremes. All other numbers apply at T A e 25 § C, V DD e 7.5V, V SS eb 7.5V,D.GND e A.GND e 0V as shown in the test

circuit, Figures3 and 4.

Note 3: Guaranteed and 100% production tested.

Note 4: Guaranteed (but not 100% production tested) over the operating temperature range. These limits are not used to calculate outgoing quality levels.

Timing Diagram

TL/H/6753±3

Note: To change the gain of the presently selected band, it is not necessary to send DATA 1 (Band Selection) each time.

FIGURE 1

Electrical Characteristics (Note 2) V DD e 7.5V, V SS eb 7.5V, D.GND e A.GND e 0V

SIGNAL PATH SECTION

Tested Design

Unit

Symbol

Parameter

Test Conditions

Typ

Limit

(Limit)

(Note 3)

(Note 4)

E A

Gain Error

A V e 0dB @ g 12 dB Range

0.1

0.5

dB (Max)

A V e 0dB @ g 6 dB Range

0.1

dB (Max)

A V e g 1dB @ g dB Range

0.1

0.5

0.6

dB (Max)

(R 5b or R 5c is ON)

A V e g 2dB @ g 12 dB Range

0.1

0.5

0.6

dB (Max)

(R 4b or R 4c is ON)

A V e g 3dB @ g 12 dB Range

0.1

0.5

0.6

dB (Max)

(R 3b or R 3c is ON)

A V e g 4dB @ g 12 dB Range

0.1

0.5

0.7

dB (Max)

(R 2b or R 2c is ON)

A V e g 5dB @ g 12 dB Range

0.1

0.5

0.7

dB (Max)

(R 1b or R 1c is ON)

A V e g 9dB @ g 12 dB Range

0.2

1.3

dB (Max)

(R 0b or R 0c is ON)

THD

Total Harmonic

A V e 0dB @ g 12 dB Range

0.0015

Distortion

V IN e 4V rms ,f e 1 kHz

A V e 12 dB @ g 12 dB Range

V IN e 1V rms ,f e 1 kHz

0.01

0.1

% (Max)

V IN e 1V rms ,f e 20 kHz

0.1

0.5

% (Max)

A V eb 12 dB @ g 12 dB Range

V IN e 4V rms ,f e 1 kHz

0.01

0.1

% (Max)

V IN e 4V rms ,f e 20 kHz

0.1

0.5

% (Max)

V O Max Maximum Output Voltage A V e 0dB @ g 12 dB Range

5.5

5.1

V rms (Min)

THD k 1%, f e 1 kHz

S/N

Signal to Noise Ratio

A V e 0dB @ g 12 dB Range

114

V ref e 1V rms

A V e 12 dB @ g 12 dB Range

106

V ref e 1V rms

A V eb 12 dB @ g 12 dB Range

V ref e 1V rms

I LEAK Leakage Current A V e 0dB @ g 12 dB Range

(All internal switches are OFF)

Pin 2 a 3, Pin 26 500 nA (Max)

Pin 5 E Pin 11, Pin 18 E Pin 24 50 nA (Max)

Note 2; Boldface numbers apply at temperature extremes. All other numbers apply at T A e 25 § C, V DD e 7.5V, V SS eb 7.5V, D.GND e A.GND e 0V as shown in the

test circuit, Figures3 and 4.

Note 3: Guaranteed and 100% production tested.

Note 4: Guaranteed (but not 100% production tested) over the operating temperature range. These limits are not used to calculate outgoing quality levels.

116

Timing Diagrams

TL/H/6753±4

Note: To change the gain of the presently selected band, it is not necessary to send DATA 1 (Band Selection) each time.

FIGURE 2

Truth Tables

DATA I (Band Selection)

D7 D6 D5 D4 D3 D2 D1 D0

HX L L L L L L

HX L L L L L H

HX L L L L HL

HX L L L L HH

HX L L L HL L

HX L L L HL H

HX L L L HHL

HXL L L HHH

HX L L HL L L

HX L L HL L H

HX L L HL HL

HX L L HL HH

HX L L HHL L

HX L L HHL H

HXL L HHHL

HXL L HHHH

H X L H Valid Binary Input

H X H L Valid Binary Input

H X H H Valid Binary Input

uuuuw Band Code x

jklm

j DATA 1

k Don't Care

l Ch A g 6 dB/ g 12 dB Range

m Ch B g 6 dB/ g 12 dB Range

(Ch A: Band 1 E 7, Ch B: Band 8 E 14)

Ch A g 12 dB Range, Ch B g 12 dB Range, No Band Selection

Ch A g 12 dB Range, Ch B g 12 dB Range, Band 1

Ch A g 12 dB Range, Ch B g 12 dB Range, Band 2

Ch A g 12 dB Range, Ch B g 12 dB Range, Band 3

Ch A g 12 dB Range, Ch B g 12 dB Range, Band 4

Ch A g 12 dB Range, Ch B g 12 dB Range, Band 5

Ch A g 12 dB Range, Ch B g 12 dB Range, Band 6

Ch A g 12 dB Range, Ch B g 12 dB Range, Band 7

Ch A g 12 dB Range, Ch B g 12 dB Range, Band 8

Ch A g 12 dB Range, Ch B g 12 dB Range, Band 9

Ch A g 12 dB Range, Ch B g 12 dB Range, Band 10

Ch A g 12 dB Range, Ch B g 12 dB Range, Band 11

Ch A g 12 dB Range, Ch B g 12 dB Range, Band 12

Ch A g 12 dB Range, Ch B g 12 dB Range, Band 13

Ch A g 12 dB Range, Ch B g 12 dB Range, Band 14

Ch A g 12 dB Range, Ch B g 12 dB Range, No Band Selection

Ch A g 12 dB Range, Ch B g 6 dB Range, Band 1 E 14

Ch A g 6 dB Range, Ch B g 12 dB Range, Band 1 E 14

Ch A g 6 dB Range, Ch B g 6 dB Range, Band 1 E 14

DATA II (Gain Selection)

D7 D6 D5 D4 D3 D2 D1 D0

Flat

L X L L L L L L

1 dB Boost

L H H L L L L L

2 dB Boost

L H L H L L L L

3 dB Boost

L H L L H L L L

4 dB Boost

L H L L L H L L

This is the gain if the g 12 dB range is

selected by DATA I. If the g 6dB

range is selected, then the values

shown must be approximately halved.

See the characteristics curves for

more exact data.

5 dB Boost

L H L L L L H L

6 dB Boost

L H L H L L H L

7 dB Boost

L H H L H L H L

8 dB Boost

L H L H L H H L

9 dB Boost

L H L L L L L H

10 dB Boost

L H H L H L L H

11 dB Boost

L H H L H H L H

12 dB Boost

L H H L H H H H

1dB E 12 dB Cut L L

Valid Above Input

uu w Gain Code x

n DATA II

o Boost/Cut

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