FX631.PDF

CML Semiconductor Products

PRODUCT INFORMATION

FX631

Low-Voltage SPM Detector

Publication D/631/6 June 1997

Features

Detects 12kHz and 16kHz SPM

Frequencies

Low Power (3.0 Volt MIN <1.0mA)

Operation

High Speechband Rejection

Properties

Tone-Follower and Packet Mode

Outputs

Applications

Complex and/or Simple

Telephone Systems

Call-Charge/-Logging

Systems

XTAL/CLOCK

CLOCK

OUT

CLOCK IN

V SS

XTAL/CLOCK

OSCILLATOR

CLOCK

DIVIDERS

SYSTEM

XTAL

V DD

TONE FOLLOWER

OUTPUT

FX631

SYSTEM

TONE

FOLLOWER

LOGIC

SIGNAL

IN (-)

INPUT AMP

12kHz/16kHz

PERIOD

MEASURE

+20dB

SIGNAL

IN (+)

LEVEL DETECTOR

DIVIDER

PACKET MODE

OUTPUT

AMP OUT

PACKET

TONE

LOGIC

SYSTEM

V BIAS

Fig.1 Functional Block Diagram

Brief Description

The FX631 is a low-power, system-selectable

Subscriber Pulse Metering (SPM) detector to indicate

the presence, on a telephone line, of both 12kHz and

16kHz telephone call-charge frequencies.

Deriving its input directly from the telephone line,

input amplitude/sensitivities are component adjustable

to the user's national ‘Must/Must-Not Decode’

specifications via an on-chip input amplifier, whilst the

12kHz and 16kHz frequency limits are accurately

defined by the use of an external 3.579545MHz

telephone-system Xtal or clock-pulse input.

The FX631, which demonstrates high 12kHz and

16kHz performance in the presence of both voice and

noise, can operate from either a single or differential

analogue signal input from which it will produce two

individual logic outputs.

1. Tone Follower Output - A 'tone-following' logic

output producing a “Low” level for the period of a

correct decode and a “High” level for a bad

decode or N OTONE .

2. Packet (Cumulative Tone) Mode Output - To

respond and de-respond after a cumulative 40ms

of good tone (or N OTONE ) in any 48ms period.

This process will ignore small fluctuations or

fades of a valid frequency input and is available

for µProcessor ‘Wake-Up’, Minimum tone

detection, N OTONE indication or transient

avoidance.

This system (12kHz/16kHz) selectable microcircuit,

which may be line-powered, is available in 16-pin plastic

DIL and surface mount SOIC and 24-pin plastic SSOP

packages.

(12kHz/16kHz)

Pin Number

Function

FX631

DW/P

Xtal/Clock: The inp ut to the on-chip clock oscillator; for use with a 3.579545MHz Xtal in

conjunction with the Xtal output (see Figure 2); circuit components are on chip. Using this

mode of clock operation, the Clock Out pin should be connected directly to the Clock In pin. If

a clock pulse input is employed to the Clock In pin, this pin must be connected directly to V DD

(see Figure 2).

2.3 Pin Function Description

XTAL The input of the oscillator inverter.

Xtal: The output of the on-chip clock oscillator inverter.

CLKIN The input to the internal clock divider circuitry.

When a 3.579545MHz crystal is used, it should be connected across XTAL & XTAL and XTAL

should be directly connected to CLKIN. No other external components are necessary because

the other oscillator components (capacitor, resistor) are on chip.

When an externally available clock signal is used, it should be inserted at CLKIN. XTAL should

be tied to VDD or Vss and XTAL should be left open circuit.

Clock In: The 3.579545MHz clock pulse input to the internal clock-dividers. If a clock pulse

input is employed, the Xtal/Clock input (Pin 1) should be connected to V DD . See Figure 2.

SYSTEM A logic input pin which controls whether the device detects 12Khz SPM tones (logic 1)

or 16Khz SPM tones (logic 0). It has an internal 1 Mohm pull- up resistor (l 2Khz).

V BIAS : The output of the on-chip analogue bias circuitry. Held internally at V DD /2, this pin should

be decoupled to V SS (see Figure 2).

NEGIP The negative input, positive input and output respectively of the gain adjusting POSIP

amplifier.

AMPOP

External components are used in conjunction with the op -amp according to the required level

sensitivity and depending on whether the incoming signal is differential or common mode.

V SS : Negative supply rail (GND).

Signal In (+):

VDD The power supply, ground and filter bias pins respectively.

VSS

BIAS Voo and bias should each be de- coupled, via a 1 .0@F capacitor, to VSS.

The positive and negative signal inputs to, and the output from, the input gain

adjusting signal amplifier. Refer to the graph in Figure 4 for guidance on

setting level sensitivities to national specifications, and the selection of gain

adjusting components.

Signal In (-):

Amp Out:

TTFOP TRUE TONE FOLLOWER OUTPUT. This is the pin that responds and de-

responds within 4ms of a good tone appearing or disappearing.

Tone Follower Output: This output provides a logic “0” (Low) for the period of a detected

tone, and a logic “1” (High) for N OTONE detection. See Figure 7.

· logic 0 represents ‘detect’ and logic 1 represents ‘not detect’.

Packet Mode Output: A logic output that will be available after a cumulation of 40ms of 'good'

tone has been received. This packet mode tone follower will only respond when a tone

frequency of sufficient quality has been received for sufficient time, i.e. a cumulation of 40ms in

any 48ms, short tone bursts or breaks will be ignored. This output provides a logic “0” (Low)

for a detected tone and a logic “1” (High) for N OTONE detection. See Figure 7.

DTFOP This is the output of the ‘delayed tone follower’ block.

It will respond when 40ms of good tone has been received within any 48ms window. The 48ms

is divided into 24 ‘packets’ of 2ms each (16Khz mode) or 15 ‘packets’ of 2.667ms each (12Khz

mode). Each packet represents 32 cycles of SPM frequency. The window is a shifting window,

ie. the 48ms window is assessed every 2ms (16Khz mode) or 2.667ms (12Khz). If the

necessary number of good packets are consecutive, the output will respond in the minimum

time of 40ms.

System: The logic input to select device operation to either 12kHz (logic “1” - High) or 16kHz

(logic “0” - Low) SPM systems. This input has an internal 1M

pullup resistor (12kHz).

V DD : Positive supply rail. A single, stable power supply is required. Critical levels and voltages

within the FX631 are dependant upon this supply. This pin should be decoupled to V SS

by a capacitor mounted close to the pin.

Note that if this device is ‘line’ powered, the resulting supply must be stable. See notes on

Microcircuit Protection from high and spurious line voltages.

· logic 0 represents ‘detect’ and logic 1 represents ‘not detect’.

2, 3,

7, 9,

10, 11,

14,

15, 16,

22, 23

5, 6,

No internal connection, leave open circuit.

XTALN The output of the oscillator inverter

Clock Out: The buffered output of the on-chip clock oscillator inverter. If a Xtal input is

employed this output should be connected directly to the Clock In pin.

It is thus like an envelope of the SPM tone.

Application Information

External Components

V DD

C 1

XTAL/CLOCK

X TAL/CLOCK

V SS

V DD

X 1

For use with a Clock Pulse input

- Remove Xtal (X 1 )

- Connect Pin 1 to V DD

- Remove link (Pins 3/4)

- Input clock pulses to CLOCK IN

XTAL

SYSTEM

CLOCK OUT

PACKET MODE OUTPUT

TONE FOLLOWER OUTPUT

CLOCK IN

FX631DW

AMP OUT

R 1

V BIAS

SIGNAL IN (-)

C 3

V SS

SIGNAL IN ( + )

R 2

C 4

R 3

R 4

C 2

V SS

Fig.2 Recommended External Components - Differential Input Mode

Component

Value

External Components

1. The values of the Input Amp gain components

illustrated are calculated using the Input Gain

Calculation Graphs (Figures 4 and 5).

Whilst calculating input gain components, for

correct operation, it is recommended that the

values of resistors R 1 and R 4 are always greater

than, or equal to, 33k

R 1

R FEEDBACK

R 2

R IN (+)

R 4

R BIAS

C 1

1.0µF ±20%

C 2

1.0µF ±20%

C 3

C IN (-)

C 4

C IN (+)

X 1

3.579545MHz

2. Refer to following pages for advice on Microcircuit

Protection from high and spurious line voltages.

Differential Input

Common Mode Input

INPUT AMP

Tip (a)

Ring (b)

V BIAS

V SS

Fig.3 Example Input Configurations

R 3

R IN (-)

Application Information ......

-10

-15

-20

MUST DECODE LEVEL

-25

-30

MUST NOT DECODE LEVEL

-35

-40

-45

MINIMUM AMPLIFIER GAIN

MAXIMUM AMPLIFIER GAIN

-50

-20

-15

-10

-5

AMPLIFIER GAIN (dB)

V DD =3.3(+/-0.1)VOLTS TEMP= -40 o Cto+85 o C

Fig.4 Input Gain Calculation Graph for V DD = 3.3V

Fig.5 Input Gain Calculation Graph for V DD = 5.0V

-25

Application Information ......

Input Gain Calculation

The input amplifier, with its external circuitry, is

provided on-chip to set the sensitivity of the FX631 to

conform to the user's national level specification with

regard to ‘Must’ and ‘Must-Not’ decode signal levels.

With reference to the graphs in Figures 4 and 5,

the following steps will assist in the determination of

the required gain/attenuation.

Input Gain Components

With reference to the gain components shown in Figures

2 and 3.

The user should calculate and select external

components (R 1 , R 2 /C 3 , R 3 /C 4 , R 4 ) to provide an amplifier

gain within the limits obtained in Steps 2 and 3.

Component tolerances should not move the gain-figure

outside these limits.

It is recommended that the designed gain is near the

centre of the calculated range. The graphs in Figures 4 and

5 are for the calculation of input gain components for an

FX631 using a V DD of 3.3 (±0.1) or 5.0 (±0.5) volts

respectively.

Step 1

Draw two horizontal lines from the Y-axis (Signal

Levels (dB)).

The upper line will represent the required ‘Must’

decode level.

The lower line will represent the required ‘Must-

Not’ decode level.

Use this area to keep a permanent record

of your calculated gains and components

Step 2

Mark the intersection of the upper horizontal line

and the upper sloping line; drop a vertical line

from this point to the X-axis (Amplifier Gain (dB)).

The point where the vertical line meets the X-axis

will indicate the MINIMUM Input Amp gain

required for reliable decoding of valid signals.

Step 3

Mark the intersection of the lower horizontal line

and the lower sloping line; drop a vertical line from

this point to the X-axis.

The point where the vertical line meets the X-axis

will indicate the MAXIMUM allowable Input Amp

gain.

Input signals at or below the ‘Must-Not’ decode

level will not be detected as long as the amplifier

gain is no higher than this level.

Select the gain components as described

opposite.

Implementation Notes

Aliasing

Due to the switched-capacitor filters employed in the

FX631, care should be taken, with the chosen external

components, to avoid the effects of alias distortion.

Microcircuit Protection

Telephone systems may have high d.c. and a.c.

voltages present on the line. If the FX631 is part of a host

equipment that has its own signal input protection circuitry,

there will be no need for further protection as long as the

voltage on any pin is limited to within V DD + 0.3V and

V SS -0.3V.

If the host system does not have input protection, or

there are signals present outside the device's specified

limits, the FX631 will require protection diodes at its signal

inputs (+ and -). The breakdown voltage of capacitors and

the peak inverse voltage of the diodes must be sufficient to

withstand the sum of the d.c. voltages plus all expected

signal peaks.

Possible Alias Frequencies:

12kHz Mode = 52kHz

16kHz Mode = 69kHz

If these alias frequencies are liable to cause problems and/

or interference, it is recommended that anti-alias capacitors

are employed across input resistors R 1 and R 4 .

Values of anti-alias capacitors should be chosen so as to

provide a highpass cutoff frequency, in conjunction with R 1

(R 4 ) of approximately 20kHz to 25kHz (12kHz system) or

25kHz to 30kHz (16kHz system).

i.e. C = 1

2 x p

x f 0 x R 1

When anti-alias capacitors are used, allowance must be

made for reduced gain at the SPM frequency (12kHz or

16kHz).

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika: