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54F/74F545 Octal Bidirectional Transceiver with TRI-STATE(RM) Outputs
May 1995
54F/74F545 Octal Bidirectional
Transceiver with TRI-STATE
É
Outputs
General Description
The 'F545 is an 8-bit, TRI-STATE, high-speed transceiver. It
provides bidirectional drive for bus-oriented microprocessor
and digital communications systems. Straight through bidi-
rectional transceivers are featured, with 24 mA (20 mA Mil)
bus drive capability on the A ports and 64 mA (48 mA Mil)
bus drive capability on the B por
ts
.
One input, Transmit/Receive (T/R) determines the direction
of logic signals through the bidirectional transceiver. Trans-
mit enables data from A ports to B ports; Receive enables
data from B ports to A ports. The Output Enable input dis-
ables both A and B ports by placing them in a TRI-STATE
condition.
Features
Y
Higher drive than 8304
Y
8-bit bidirectional data flow reduces system package
count
Y
TRI-STATE inputs/outputs for interfacing with bus-ori-
ented systems
Y
24 mA (20 mA Mil) and 64 mA (48 mA Mil) bus drive
capability on A and B ports, respectively
Y
Transmit/Receive and Output Enable simplify control
logic
Y
Guaranteed 4000V minimum ESD protection
Y
Pin for Pin compatible with Intel 8286
Commercial
Military
Package
Package Description
Number
74F545PC
N20A 20-Lead (0.300
×
Wide) Molded Dual-In-Line
54F545DM (Note 2)
J20A 20-Lead Ceramic Dual-In-Line
74F545SC (Note 1)
M20B 20-Lead (0.300
×
Wide) Molded Small Outline, JEDEC
74F545SJ (Note 1)
M20D 20-Lead (0.300
×
Wide) Molded Small Outline, EIAJ
54F545FM (Note 2) W20A 20-Lead Cerpack
54F545LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13
×
reel. Use suffix
e
SCX and SJX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix
e
DMQB, FMQB and LMQB.
Logic Symbols
TL/F/9556±3
IEEE/IEC
TL/F/9556±5
TRI-STATE
É
is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9556
RRD-B30M105/Printed in U. S. A.
Connection Diagrams
Pin Assignment for
DIP, SOIC and Flatpak
Pin Assignment
for LCC
TL/F/9556±2
TL/F/9556±1
Truth Table
Inputs
Outputs
OE T/R
L L Bus B Data to Bus A
L H Bus A Data to Bus B
H X High Z
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Z
e
High Impedance
Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L. Input I
IH
/I
IL
HIGH/LOW Output I
OH
/I
OL
O
E
Output Enable Input (Active LOW) 1.0/2.0
20
m
A/
b
1.2 mA
T/R
Transmit/Receive Input
1.0/2.0
20
m
A/
b
1.2 mA
A
0
±A
7
Side A TRI-STATE Inputs or
3.5/1.083
70
m
A/
b
650
m
A
TRI-STATE Outputs
150/40 (33.3)
b
3 mA/24 mA (20 mA)
B
0
±B
7
Side B TRI-STATE Inputs or
3.5/1.083
70
m
A/
b
650
m
A
TRI-STATE Outputs
600/106.6 (80)
b
12 mA/64 mA (48 mA)
2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
b
65
§
Cto
a
150
§
C
Ambient Temperature under Bias
b
55
§
Cto
a
125
§
C
Junction Temperature under Bias
b
55
§
Cto
a
175
§
C
Plastic
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
b
55
§
Cto
a
150
§
C
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
b
55
§
Cto
a
125
§
C
V
CC
Pin Potential to
Ground Pin
Commercial
0
§
Cto
a
70
§
C
b
0.5V to
a
7.0V
Supply Voltage
Military
Input Voltage (Note 2)
b
0.5V to
a
7.0V
a
4.5V to
a
5.5V
Commercial
a
4.5V to
a
5.5V
Input Current (Note 2)
b
30 mA to
a
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
b
0.5V to V
CC
TRI-STATE Output
b
0.5V to
a
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min)
4000V
DC Electrical Characteristics
Symbol
Parameter
54F/74F
Units V
CC
Conditions
Min Typ Max
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as
a LO
W
S
ignal
V
CD
Input Clamp Diode Voltage
b
1.2 V Min I
IN
eb
18 mA (OE, T/R)
V
OH
Output HIGH
54F 10% V
CC
2.5
I
OH
eb
1mA(A
n
)
Voltage
54F 10% V
CC
2.4
I
OH
eb
3mA(A
n
)
54F 10% V
CC
2.0
I
OH
eb
12 mA (B
n
)
74F 10% V
CC
2.5
I
OH
eb
1mA(A
n
)
74F 10% V
CC
2.4
V Min
I
OH
eb
3mA(A
n
)
74F 10% V
CC
2.0
I
OH
eb
15 mA (B
n
)
74F 5% V
CC
2.7
I
OH
eb
1mA(A
n
)
74F 5% V
CC
2.7
I
OH
eb
3mA(A
n
)
V
OL
Output LOW
54F 10% V
CC
0.5
I
OL
e
20 mA (A
n
)
Voltage
54F 10% V
CC
0.55
I
OL
e
48 mA (B
n
)
V Min
74F 10% V
CC
0.5
I
OL
e
24 mA (A
n
)
74F 10% V
CC
0.55
I
OL
e
64 m
A (B
n
)
I
IH
Input HIGH
54F
20.0
m
A Max
V
IN
e
2.7V (OE, T/R)
Current
74F
5.0
I
BVI
Input HIGH Current 54F
100
m
A Max
V
IN
e
7.0V (OE, T/R)
Breakdown Test
74F
7.0
I
BVIT
Input HIGH Current 54F
1.0
mA Max
V
IN
e
5.5V (A
n
,B
n
)
Breakdown (I/O)
74F
0.5
I
CEX
Output HIGH
54F
250
m
A Max
V
OUT
e
V
CC
Leakage Current
74F
50
V
ID
Input Leakage
74F
4.75
V 0.0
I
ID
e
1.9
m
A
Test
All Other Pins Grounded
I
OD
Output Leakage
74F
3.75
m
A 0.0
V
IOD
e
150 mV
Circuit Current
All Other Pin
s G
rou
nd
ed
I
IL
Input LOW Current
b
1.2 mA Max V
IN
e
0.5V (OE, T/R)
I
IH
a
I
OZH
Output Leakage Current
70
m
A Max V
OUT
e
2.7V (A
n
,B
n
)
I
IL
a
I
OZL
Output Leakage Current
b
650
m
A Max V
OUT
e
0.5V (A
n
,B
n
)
I
OS
Output Short-Circuit Current
b
60
b
150
mA Max
V
OUT
e
0V (A
n
)
b
100
b
225
V
OUT
e
0V (B
n
)
3
DC Electrical Characteristics
(Continued)
Symbol
Parameter
54F/74F
Units V
CC
Conditions
Min Typ Max
I
ZZ
Bus Drainage Test
500
m
A
0.0V V
OUT
e
5.25V
I
CCH
Power Supply Current
70
90 mA Max V
O
e
HIGH
I
CCL
Power Supply Current
95
120 mA Max V
O
e
LOW
I
CCZ
Power Supply Current
85
110 mA Max V
O
e
HIGH Z
AC Electrical Characteristics
74F
54F
74F
T
A
ea
25
§
C
T
A
,V
CC
e
Mil
T
A
,V
CC
e
Com
Symbol
Parameter
V
CC
ea
5.0V
C
L
e
50 pF
C
L
e
50 pF
Units
C
L
e
50 pF
Min
Typ Max Min Max Min Max
t
PLH
Propagation Delay
2.5
4.2
6.0
2.0
7.5
2.5
7.0
ns
t
PHL
A
n
to B
n
or B
n
to A
n
2.5
4.6
6.0
2.0
7.5
2.5
7.0
t
PZH
Output Enable Time
3.0
5.3
7.0
2.5
9.0
3.0
8.0
t
PZL
3.5
6.0
8.0
3.0
10.0
3.5
9.0
ns
t
PHZ
Output Disable Time
3.0
5.0
6.5
2.5
9.0
3.0
7.5
t
PLZ
2.0
5.0
6.5
2.0
10.0
2.0
7.5
Logic Diagram
TL/F/9556±4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 545 S C X
Temperature Range Family
Special Variations
74F
e
Commercial
QB
e
Military grade device with
54F
e
Military
environmental and burn-in
processing
Device Type
X
e
Devices shipped in 13
×
reel
Package Code
Temperature Range
P
e
Plastic DIP
C
e
Commercial (0
§
Cto
a
70
§
C)
D
e
Ceramic DIP
M
e
Military (
b
55
§
Cto
a
125
§
C)
F
e
Flatpak
L
e
Leadless Chip Carrier (LCC)
S
e
Small Outline SOIC JEDEC
SJ
e
Small Outline SOIC EIAJ
4
Physical Dimensions
inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
5
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