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AD9850 Data Sheet
a
CMOS, 125 MHz
Complete DDS Synthesizer
AD9850
FEATURES
125 MHz Clock Rate
On-Chip High Performance DAC and High Speed
Comparator
DAC SFDR > 50 dB @ 40 MHz A OUT
32-Bit Frequency Tuning Word
Simplified Control Interface: Parallel Byte or Serial
Loading Format
Phase Modulation Capability
+3.3 V or +5 V Single Supply Operation
Low Power: 380 mW @ 125 MHz (+5 V)
Low Power: 155 mW @ 110 MHz (+3.3 V)
Power-Down Function
Ultrasmall 28-Lead SSOP Packaging
FUNCTIONAL BLOCK DIAGRAM
+V S
GND
REF
CLOCK IN
MASTER
RESET
DAC R SET
HIGH SPEED
DDS
10-BIT
DAC
ANALOG
OUT
PHASE
AND
CONTROL
WORDS
FREQUENCY
UPDATE/
DATA REGISTER
RESET
32-BIT
TUNING
WORD
ANALOG
IN
FREQUENCY/PHASE
DATA REGISTER
CLOCK OUT
CLOCK OUT
WORD LOAD
CLOCK
DATA INPUT REGISTER
COMPARATOR
SERIAL
LOAD
PARALLEL
LOAD
AD9850
APPLICATIONS
Frequency/Phase–Agile Sine-Wave Synthesis
Clock Recovery and Locking Circuitry for Digital
Communications
Digitally Controlled ADC Encode Generator
Agile Local Oscillator Applications
8-BITS
5 LOADS
FREQUENCY, PHASE, AND CONTROL
DATA INPUT
1-BIT
40 LOADS
GENERAL DESCRIPTION
The AD9850 is a highly integrated device that uses advanced
DDS technology coupled with an internal high speed, high
performance, D/A converter and comparator, to form a com-
plete digitally programmable frequency synthesizer and clock
generator function. When referenced to an accurate clock
source, the AD9850 generates a spectrally pure, frequency/
phase-programmable, analog output sine wave. This sine wave
can be used directly as a frequency source or converted to a
square wave for agile-clock generator applications. The AD9850’s
innovative high speed DDS core provides a 32-bit frequency
tuning word, which results in an output tuning resolution of
0.0291 Hz, for a 125 MHz reference clock input. The
AD9850’s circuit architecture allows the generation of output
frequencies of up to one-half the reference clock frequency (or
62.5 MHz), and the output frequency can be digitally changed
(asynchronously) at a rate of up to 23 million new frequencies
per second. The device also provides five bits of digitally
controlled phase modulation, which enables phase shifting of its
output in increments of 180
combination thereof. The AD9850 also contains a high speed
comparator that can be configured to accept the (externally)
filtered output of the DAC to generate a low jitter square wave
output. This facilitates the device’s use as an agile clock gen-
erator function.
The frequency tuning, control, and phase modulation words are
loaded into the AD9850 via a parallel byte or serial loading
format. The parallel load format consists of five iterative loads
of an 8-bit control word (byte). The first byte controls phase
modulation, power-down enable, and loading format; bytes 2–5
comprise the 32-bit frequency tuning word. Serial loading is
accomplished via a 40-bit serial data stream on a single pin. The
AD9850 Complete-DDS uses advanced CMOS technology to
provide this breakthrough level of functionality and performance
on just 155 mW of power dissipation (+3.3 V supply).
The AD9850 is available in a space saving 28-lead SSOP, sur-
face mount package. It is specified to operate over the extended
industrial temperature range of –40°C to +85°C.
°
, 90
°
, 45
, 22.5
°
, 11.25
°
and any
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
°
423462232.005.png 423462232.006.png
AD9850–SPECIFICATIONS
(V S = +5 V
5% except as noted, R SET = 3.9 k
)
AD9850BRS
Parameter
Temp
Test Level
Min
Typ
Max
Units
CLOCK INPUT CHARACTERISTICS
Frequency Range
+5 V Supply
Full
IV
1
125
MHz
+3.3 V Supply
Full
IV
1
110
MHz
Pulsewidth High/Low
+5 V Supply
+25°C
IV
3.2
ns
+3.3 V Supply
+25°C
IV
4.1
ns
DAC OUTPUT CHARACTERISTICS
Full-Scale Output Current
R SET = 3.9 k
Ω
+25
°
C
V
10.24
mA
R SET = 1.95 k
Ω
+25
°
C
V
20.48
mA
Gain Error
+25
°
C
I
–10
+10
% FS
Gain Temperature Coefficient
Full
V
150
ppm/
°
C
Output Offset
+25
°
CI
10
µ
A
Output Offset Temperature Coefficient
Full
V
50
nA/
°
C
Differential Nonlinearity
+25
°
C
I
0.5
0.75
LSB
Integral Nonlinearity
+25
°
C
I
0.5
1
LSB
Output Slew Rate (50
Ω
, 2 pF Load)
+25
°
C
V
400
V/
µ
s
Output Impedance
+25
°
C
IV
50
120
k
Ω
Output Capacitance
+25
°
CIV
8
pF
Voltage Compliance
+25
°
C
I
1.5
V
Spurious-Free Dynamic Range (SFDR):
Wideband (Nyquist Bandwidth)
1 MHz Analog Out
+25
°
C
IV
63
72
dBc
20 MHz Analog Out
+25
°
C
IV
50
58
dBc
40 MHz Analog Out
+25
°
C
IV
46
54
dBc
Narrowband
40.13579 MHz
±
50 kHz
+25
°
C
IV
80
dBc
40.13579 MHz
±
200 kHz
+25
°
C
IV
77
dBc
4.513579 MHz
±
50 kHz/20.5 MHz CLK
+25
°
C
IV
84
dBc
4.513579 MHz
±
200 kHz/20.5 MHz CLK
+25
°
C
IV
84
dBc
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance
+25°CV
3
pF
Input Resistance
+25°C
IV
500
kΩ
Input Current
+25°C
I
–12
+12
µA
Input Voltage Range
+25°CIV
0
V DD
V
Comparator Offset*
Full
VI
30
30
mV
COMPARATOR OUTPUT CHARACTERISTICS
Logic “1” Voltage +5 V Supply
Full
VI
+4.8
V
Logic “1” Voltage +3.3 V Supply
Full
VI
+3.1
V
Logic “0” Voltage
Full
VI
+0.4
V
Propagation Delay, +5 V Supply (15 pF Load)
+25°C
V
5.5
ns
Propagation Delay, +3.3 V Supply (15 pF Load)
+25°CV
7
ns
Rise/Fall Time, +5 V Supply (15 pF Load)
+25°CV
3
ns
Rise/Fall Time, +3.3 V Supply (15 pF Load)
+25°C
V
3.5
ns
Output Jitter (p-p)
+25°CV
80
ps
CLOCK OUTPUT CHARACTERISTICS
Clock Output Duty Cycle (Clk Gen. Config.)
+25
°
C
IV
50
±
10
%
–2–
REV. E
423462232.007.png
AD9850
AD9850BRS
Parameter
Temp
Test Level
Min Typ Max
Units
CMOS LOGIC INPUTS (Including CLKIN)
Logic “1” Voltage, +5 V Supply
+25°C
I
3.5
V
Logic “1” Voltage, +3.3 V Supply
+25°C
I
3.0
V
Logic “0” Voltage
+25°C
I
0.4
V
Logic “1” Current
+25°CI
12
µA
Logic “0” Current
+25°CI
12
µA
Input Capacitance
+25°CV
3
pF
POWER SUPPLY (A OUT = 1/3 CLKIN)
+V S Current @:
62.5 MHz Clock, +3.3 V Supply
Full
VI
30
48
mA
110 MHz Clock, +3.3 V Supply
Full
VI
47
60
mA
62.5 MHz Clock, +5 V Supply
Full
VI
44
64
mA
125 MHz Clock, +5 V Supply
Full
VI
76
96
mA
P DISS @:
62.5 MHz Clock, +3.3 V Supply
Full
VI
100 160
mW
110 MHz Clock, +3.3 V Supply
Full
VI
155 200
mW
62.5 MHz Clock, +5 V Supply
Full
VI
220 320
mW
125 MHz Clock, +5 V Supply
Full
VI
380 480
mW
P DISS Power-Down Mode
+5 V Supply
Full
V
30
mW
+3.3 V Supply
Full
V
10
mW
NOTES
*Tested by measuring output duty cycle variation.
Specifications subject to change without notice.
TIMING CHARACTERISTICS*
(V S = +5 V
5% except as noted, R SET = 3.9 k
)
AD9850BRS
Parameter
Temp
Test Level
Min
Typ Max
Units
t DS (Data Setup Time)
Full
IV
3.5
ns
t DH (Data Hold Time)
Full
IV
3.5
ns
t WH (W_CLK min. Pulsewidth High)
Full
IV
3.5
ns
t WL (W_CLK min. Pulsewidth Low)
Full
IV
3.5
ns
t WD (W_CLK Delay After FQ_UD)
Full
IV
7.0
ns
t CD (CLKIN Delay After FQ_UD)
Full
IV
3.5
ns
t FH (FQ_UD High)
Full
IV
7.0
ns
t FL (FQ_UD Low)
Full
IV
7.0
ns
t CF (Output Latency from FQ_UD)
Frequency Change
Full
IV
18
CLKIN Cycles
Phase Change
Full
IV
13
CLKIN Cycles
t FD (FQ_UD Min. Delay After W_CLK)
Full
IV
7.0
ns
t RH (CLKIN Delay After RESET Rising Edge)
Full
IV
3.5
ns
t RL (RESET Falling Edge After CLKIN)
Full
IV
3.5
ns
t RS (Minimum RESET Width)
Full
IV
5
CLKIN Cycles
t OL (RESET Output Latency)
Full
IV
13
CLKIN Cycles
t RR (Recovery from RESET)
Full
IV
2
CLKIN Cycles
Wake-Up Time from Power-Down Mode
+25°CV
5
µs
NOTES
*Control functions are asynchronous with CLKIN.
Specifications subject to change without notice.
REV. E
–3–
423462232.008.png
AD9850
C
V DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +V S
Digital Output Continuous Current . . . . . . . . . . . . . . . 5 mA
DAC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Storage Temperature . . . . . . . . . . . . . . . . . . –65
°
EXPLANATION OF TEST LEVELS
Test Level
I – 100% Production Tested.
III – Sample Tested Only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at +25
°
C to +150
°
C
Operating Temperature . . . . . . . . . . . . . . . . . –40
°
C to +85
°
C
C.
100% production tested at temperature extremes for
military temperature devices; guaranteed by design and
characterization testing for industrial devices.
°
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . +300
°
C
C/W
*Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect
device reliability.
θ JA Thermal Impedance . . . . . . . . . . . . . . . . . . 82
°
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9850 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Application Note : Users are cautioned not to apply digital input signals prior to power-up of this
device. Doing so may r esult in a latch-up condition.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD9850BRS
–40°C to +85°C
Shrink Small Outline (SSOP)
RS-28
–4–
REV. E
ABSOLUTE MAXIMUM RATINGS*
Maximum Junction Temperature . . . . . . . . . . . . . . . +165
SSOP
423462232.001.png 423462232.002.png 423462232.003.png
AD9850
Table I. Lead Function Descriptions
Pin
No.
Mnemonic
Function
4–1,
D0–D7
8-Bit Data Input. This is the 8-bit data port for iteratively loading the 32-bit frequency and 8-bit phase/
28–25
control word. D7 = MSB; D0 = LSB. D7 (Pin 25) also serves as the input pin for the 40-bit serial data word.
5, 24
DGND
Digital Ground. These are the ground return leads for the digital circuitry.
6, 23
DVDD
Supply Voltage Leads for digital circuitry.
7
W_CLK
Word Load Clock. This clock is used to load the parallel or serial frequency/phase/control words.
8
FQ_UD
Frequency Update. On the rising edge of this clock, the DDS will update to the frequency (or phase)
loaded in the data input register, it then resets the pointer to Word 0.
9
CLKIN
Reference Clock Input. This may be a continuous CMOS-level pulse train or sine input biased at
1/2 V supply. The rising edge of this clock initiates operation.
10, 19 AGND
Analog Ground. These leads are the ground return for the analog circuitry (DAC and comparator).
11, 18 AVDD
Supply Voltage for the analog circuitry (DAC and comparator).
12
R SET
This is the DAC’s external R SET connection. This resistor value sets the DAC full-scale output current. For
normal applications ( F S I OUT = 10 mA ), the value for R SET is 3.9 kΩ connected to ground. The R SET /I OUT
relationship is: I OUT = 32 (1.248 V/R SET ).
13
QOUTB
Output Complement. This is the comparator’s complement output.
14
QOUT
Output True. This is the comparator’s true output.
15
VINN
Inverting Voltage Input. This is the comparator’s negative input.
16
VINP
Noninverting Voltage Input. This is the comparator’s positive input.
17
DACBL (NC) DAC Baseline. This is the DAC baseline voltage reference; this lead is internally bypassed and should
normally be considered a “no connect” for optimum performance.
20
IOUTB
The Complementary Analog Output of the DAC.
21
IOUT
Analog Current Output of the DAC.
22
RESET
Reset. This is the master reset function; when set high it clears all registers (except the input register) and
the DAC output will go to Cosine 0 after additional clock cycles—see Figure 19.
PIN CONFIGURATIONS
D3
1
2
3
4
28
27
26
25
24
23
22
21
D4
D2
D1
LSB D0
D5
D6
D7 MSB/SERIAL LOAD
DGND
DVDD
W CLK
FQ UD
CLKIN
AGND
5
DGND
6
DVDD
AD9850
7
RESET
TOP VIEW
(Not to Scale)
8
IOUT
9
20
19
18
IOUTB
10
AGND
AVDD
R SET
QOUTB
QOUT
11
AVDD
12
17
16
15
DACBL (NC)
13
VINP
14
VINN
NC = NO CONNECT
REV. E
–5–
423462232.004.png

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