DS_FT232BL.pdf

FT232BL USB UART ( USB - Serial) I.C.

The FT232BL is the lead free version of the 2 nd generation of FTDI’s popular USB UART I.C. This device not only

adds extra functionality to its FT8U232AM predecessor and reduces external component count, but also maintains a

high degree of pin compatibility with the original, making it easy to upgrade or cost reduce existing designs as well as

increasing the potential for using the device in new application areas.

1.0 Features

HARDWARE FEATURES

• Single Chip USB  Asynchronous Serial Data

Transfer

• Full Handshaking & Modem Interface Signals

• UART I/F Supports 7 / 8 Bit Data, 1 / 2 Stop Bits

and Odd/Even/Mark/Space/No Parity

• Data rate 300 => 3M Baud (TTL)

• Data rate 300 => 1M Baud (RS232)

• Data rate 300 => 3M Baud (RS422/RS485)

• 384 Byte Receive Buffer / 128 Byte Transmit Buffer

for high data throughput

• Adjustable RX buffer timeout

• Fully Assisted Hardware or X-On / X-Off

Handshaking

• In-built support for event characters and line break

condition

• Auto Transmit Buffer control for RS485

• Support for USB Suspend / Resume through

SLEEP# and RI# pins

• Support for high power USB Bus powered devices

through PWREN# pin

• Integrated level converter on UART and control

signals for interfacing to 5V and 3.3V logic

• Integrated 3.3V regulator for USB IO

• Integrated Power-On-Reset circuit

• Integrated 6MHz – 48Mhz clock multiplier PLL

• USB Bulk or Isochronous data transfer modes

• 4.35V to 5.25V single supply operation

• UHCI / OHCI / EHCI host controller compatible

• USB 1.1 and USB 2.0 compatible

• USB VID, PID, Serial Number and Product

Description strings in external EEPROM

• EEPROM programmable on-board via USB

• Compact Lead free RoHS compliant 32-LD LQFP

package.

VIRTUAL COM PORT (VCP) DRIVERS for

- Windows 98 and Windows 98 SE

- Windows 2000 / ME / Server 2003 / XP

- Windows XP 64 Bit

- Windows XP Embedded

- Windows CE 4.2

- MAC OS-8 and OS-9

- MAC OS-X

- Linux 2.40 and greater

D2XX (USB Direct Drivers + DLL S/W Interface)

- Windows 98 and Windows 98 SE

- Windows 2000 / ME / Server 2003 / XP

- Windows XP 64 Bit

- Windows XP Embedded

- Windows CE 4.2

- Linux 2.40 and greater

APPLICATION AREAS

- USB  RS232 Converters

- USB  RS422 / RS485 Converters

- Upgrading RS232 Legacy Peripherals to USB

- Cellular and Cordless Phone USB data transfer

cables and interfaces

- Interfacing MCU based designs to USB

- USB Audio and Low Bandwidth Video data transfer

- PDA  USB data transfer

- USB Smart Card Readers

- Set Top Box (S.T.B.) PC - USB interface

- USB Hardware Modems

- USB Wireless Modems

- USB Instrumentation

- USB Bar Code Readers

DS232BL Version 1.8 © Future Technology Devices Intl. Ltd. 2005 Page 1 of 25

FT232BL USB UART ( USB - Serial) I.C.

2.0 Enhancements

This section summarises the enhancements of the 2 nd generation device compared to its FT8U232AM predecessor.

For further details, consult the device pin-out description and functional descriptions.

• Integrated Power-On-Reset (POR) Circuit

The device now incorporates an internal POR

function. The existing RESET# pin is maintained

in order to allow external logic to reset the device

where required, however for many applications

this pin can now simply be hard wired to VCC. In

addition, a new reset output pin (RSTOUT#) is

provided in order to allow the new POR circuit to

provide a stable reset to external MCU and other

devices. RSTOUT# was the TEST pin on the

previous generation of devices.

This gating is now done on-chip - USBEN has

now been replaced with the new PWREN# signal

which can be used to directly drive a transistor or

P-Channel MOSFET in applications where power

switching of external circuitry is required. A new

EEPROM based option makes the device pull

gently down its UART interface lines when the

power is shut off (PWREN# is High). In this mode,

any residual voltage on external circuitry is bled to

GND when power is removed thus ensuring that

external circuitry controlled by PWREN# resets

reliably when power is restored.

• Integrated RCCLK Circuit

In the previous devices, an external RC circuit

was required to ensure that the oscillator and

clock multiplier PLL frequency was stable prior

to enabling the clock internal to the device. This

circuit is now embedded on-chip – the pin assigned

to this function is now designated as the TEST pin

and should be tied to GND for normal operation.

• Lower Suspend Current

Integration of RCCLK within the device and internal

design improvements reduce the suspend current

of the FT232BL to under 200uA (excluding the 1.5k

pull-up on USBDP) in USB suspend mode. This

allows greater margin for peripherals to meet the

USB Suspend current limit of 500uA.

• Integrated Level Converter on UART interface

and control signals

The previous devices would drive the UART and

control signals at 5V CMOS logic levels. The

new device has a separate VCC-IO pin allowing

the device to directly interface to 3.3V and other

logic families without the need for external level

converter I.C.’s

• Support for USB Isochronous Transfers

Whilst USB Bulk transfer is usually the best

choice for data transfer, the scheduling time of the

data is not guaranteed. For applications where

scheduling latency takes priority over data integrity

such as transferring audio and low bandwidth

video data, the new device now offers an option of

USB Isochronous transfer via an option bit in the

EEPROM.

• Improved Power Management control for USB

Bus Powered, high current devices

The previous devices had a USBEN pin, which

became active when the device was enumerated

by USB. To provide power control, this signal had

to be externally gated with SLEEP# and RESET#.

DS232BL Version 1.8 © Future Technology Devices Intl. Ltd. 2005 Page 2 of 25

FT232BL USB UART ( USB - Serial) I.C.

• Programmable Receive Buffer Timeout

In the previous device, the receive buffer timeout

used to ﬂush remaining data from the receive

buffer was ﬁxed at 16ms timeout. This timeout is

now programmable over USB in 1ms increments

from 1ms to 255ms, thus allowing the device to

be better optimised for protocols requiring faster

response times from short data packets.

to the device and they will be sequentially sent to

the interface at a rate controlled by the prescaler

setting. As well as allowing the device to be used

stand-alone as a general purpose IO controller for

example controlling lights, relays and switches,

some other interesting possibilities exist. For

instance, it may be possible to connect the device

to an SRAM conﬁgurable FPGA as supplied by

vendors such as Altera and Xilinx. The FPGA

device would normally be un-conﬁgured (i.e. have

no deﬁned function) at power-up. Application

software on the PC could use Bit Bang Mode to

download conﬁguration data to the FPGA which

would deﬁne its hardware function, then after

the FPGA device is conﬁgured the FT232BL can

switch back into UART interface mode to allow

the programmed FPGA device to communicate

with the PC over USB. This approach allows a

customer to create a “generic” USB peripheral

who’s hardware function can be deﬁned under

control of the application software. The FPGA

based hardware can be easily upgraded or

totally changed simply by changing the FPGA

conﬁguration data ﬁle. Application notes, software

and development modules for this application area

will be available from FTDI and other 3 rd parties.

• TXDEN Timing ﬁx

TXDEN timing has now been ﬁxed to remove the

external delay that was previously required for

RS485 applications at high baud rates. TXDEN

now works correctly during a transmit send-break

condition.

• Relaxed VCC Decoupling

The 2 nd generation devices now incorporate a level

of on-chip VCC decoupling. Though this does

not eliminate the need for external decoupling

capacitors, it signiﬁcantly improves the ease of

PCB design requirements to meet FCC, CE and

other EMI related speciﬁcations.

• Improved PreScaler Granularity

The previous version of the Prescaler supported

division by (n + 0), (n + 0.125), (n + 0.25) and

(n + 0.5) where n is an integer between 2 and

16,384 (2 14 ). To this we have added (n + 0.375),

(n + 0.625), (n + 0.75) and (n+ 0.875) which can

be used to improve the accuracy of some baud

rates and generate new baud rates which were

previously impossible (especially with higher baud

rates).

• PreScaler Divide By 1 Fix

The previous device had a problem when the

integer part of the divisor was set to 1. In the 2 nd

generation device setting the prescaler value to 1

gives a baud rate of 2 million baud and setting it

to zero gives a baud rate of 3 million baud. Non-

integer division is not supported with divisor values

of 0 and 1.

• Bit Bang Mode

The 2 nd generation device has a new option

referred to as “Bit Bang” mode. In Bit Bang mode,

the eight UART interface control lines can be

switched between UART interface mode and an

8-bit Parallel IO port. Data packets can be sent

DS232BL Version 1.8 © Future Technology Devices Intl. Ltd. 2005 Page 3 of 25

FT232BL USB UART ( USB - Serial) I.C.

• Less External Support Components

As well as eliminating the RCCLK RC network, and

for most applications the need for an external reset

circuit, we have also eliminated the requirement for

a 100K pull-up on EECS to select 6MHz operation.

When the FT232BL is being used without the

conﬁguration EEPROM, EECS, EESK and EEDATA

can now be left n/c. For circuits requiring a long

reset time (where the device is reset externally

using a reset generator I.C., or reset is controlled

by the IO port of a MCU, FPGA or ASIC device) an

external transistor circuit is no longer required as the

1.5k pull-up resistor on USBDP can be wired to the

RSTOUT# pin instead of to 3.3V. Note : RSTOUT#

drives out at 3.3V level, not at 5V VCC level. This is

the preferred conﬁguration for new designs.

• Multiple Device Support without EEPROM

When no EEPROM (or a blank or invalid

EEPROM) is attached to the device, the FT232BL

no longer gives a serial number as part of its

USB descriptor. This allows multiple devices to

be simultaneously connected to the same PC.

However, we still highly recommend that EEPROM

is used, as without serial numbers a device can

only be identiﬁed by which hub port in the USB

tree it is connected to which can change if the end

user re-plugs the device into a different port.

• Extended EEPROM Support

The previous generation of devices only supported

EEPROM of type 93C46 (64 x 16 bit). The new

devices will also work with EEPROM type 93C56

(128 x 16 bit) and 93C66 (256 x 16 bit). The extra

space is not used by the device, however it is

available for use by other external MCU / logic whilst

the FT232BL is being held in reset.

• USB 2.0 (full speed option)

A new EEPROM based option allows the FT232BL

to return a USB 2.0 device descriptor as opposed to

USB 1.1. Note : The device would be a USB 2.0 Full

Speed device (12Mb/s) as opposed to a USB 2.0

High Speed device (480Mb/s).

FT232BL USB UART ( USB - Serial) I.C.

3.0 Block Diagram (Simpliﬁed)

VCC

PWRCTL

SLEEP#

Baud Rate

Generator

48MHz

PWREN#

3V3OUT

3.3 Volt

LDO

Regulator

Dual Port TX

Buffer

128 bytes

TXD

RXD

RTS#

CTS#

DTR#

DSR#

DCD#

RI#

USBDP

Serial Interface

Engine

( SIE )

USB

Transceiver

USB

Protocol Engine

UART

FIFO Controller

UART

USBDM

TXDEN

TXLED#

RXLED#

USB DPLL

Dual Port RX

Buffer

384 Bytes

3V3OUT

EECS

EESK

EEDATA

XTOUT

48MHz

EEPROM

Interface

6MHZ

Oscillator

x8 Clock

Multiplier

XTIN

12MHz

RESET#

RESET

GENERATOR

RSTOUT#

TEST

GND

3.1 Functional Block Descriptions

• 3.3V LDO Regulator

The 3.3V LDO Regulator generates the 3.3 volt

reference voltage for driving the USB transceiver

cell output buffers. It requires an external

decoupling capacitor to be attached to the 3V3OUT

regulator output pin. It also provides 3.3V power to

the RSTOUT# pin. The main function of this block

is to power the USB Transceiver and the Reset

Generator Cells rather than to power external logic.

However, external circuitry requiring 3.3V nominal

at a current of not greater than 5mA could also

draw its power from the 3V3OUT pin if required.

and two single ended receivers provide USB data

in, SEO and USB Reset condition detection.

• USB DPLL

The USB DPLL cell locks on to the incoming NRZI

USB data and provides separate recovered clock

and data signals to the SIE block.

• 6MHz Oscillator

The 6MHz Oscillator cell generates a 6MHz

reference clock input to the x8 Clock multiplier from

an external 6MHz crystal or ceramic resonator.

• USB Transceiver

The USB Transceiver Cell provides the USB 1.1 /

USB 2.0 full-speed physical interface to the USB

cable. The output drivers provide 3.3 volt level slew

rate control signalling, whilst a differential receiver

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