Jim_Plusquel_Cadence_Tutorial.pdf

CMSC 711 CADENCE TUTORIAL Dr. Jim Plusquellic

VHDL Tutorial

This tutorial will cover the steps involved in compiling, elaborating and simulating VHDL

design ﬁles. The NC-simulator and the ncvhdl compiler under the cadence distribution will be

used for this purpose. This tutorial will cover only the command line option of running all these

tools. A later tutorial will cover the GUI option for the same.

The ncvhdl and nc-simulator binaries live under a different directory structure than the normal

directory structure used by the icfb and other related tools in the cadence distribution. So you will

require a separate .cshrc ﬁle to run these tools. The ﬁle is available at the class webpage and is

called .cshrc.sim. Copy the ﬁle in your home directory and source it whenever you want to run

VHDL simulations. The command for this is source .cshrc.sim . Source the normal .cshrc ﬁle

using the command source .cshrc when you want to run any other tools except the nc-simulators

and compilers. You will have to source one of the two ﬁles whenever you switch form icfb to

ncvhdl and vice versa.

Next step is to copy some options ﬁles and setup a directory structure. It is important that you

follow the steps involved in setting up the directory structure so that your designs are compatible

with the GUI options. Change your directory to cadence using cd cadence . Then make a directory

called vhdl in the cadence directory using mkdir vhdl . Change your working directory to vhdl

using cd vhdl . Now you will have to copy two ﬁles into this directory. One is the cds.lib ﬁle that

deﬁnes the path to some standard vhdl libraries and the hdl.var ﬁle that list the options required by

the simulator for proper operation. They are available on the course webpage and a copy is pro-

vided below. Copy these ﬁles into your vhdl directory and make sure that they have the following

lines.

cds.lib ﬁle :-

- -

- - This cds.lib ﬁle is made speciﬁcally to be used with the ldv toolset

- -

DEFINE ieee /cds/ldv/tools.sun4v/inca/ﬁles/IEEE

DEFINE std /cds/ldv/tools.sun4v/inca/ﬁles/STD

DEFINE vhdl /home/grad2/cpatel2/cadence/vhdl

Change the path in the last line to point to your vhdl directory. So you will have something like

your_home_directory/cadence/vhdl in the last line.

hdl.var ﬁle :-

DEFINE WORK vhdl

After you have copied these ﬁles in your vhdl directory you are ready to enter vhdl code. This

tutorial will cover the design and simulation of an inverter in VHDL. The directory structure that

is explained in this tutorial should be implemented for each design. The only difference will be

the names of the respective directories depending on your design names.

Prepared by :- Chintan Patel

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CMSC 711 CADENCE TUTORIAL Dr. Jim Plusquellic

We will start by making a directory called inverter in the vhdl directory. Then create a directory

called vhdl under the inverter directory. The commands required for the above steps are shown

here.

mkdir inverter

cd inverter

mkdir vhdl

cd vhdl

Now make a ﬁle called vhdl.vhd under the vhdl directory and type in your VHDL code in this

ﬁle. The code for the inverter is shown below and is also available on the course webpage. The

emacs editor under sunserver1 has a special vhdl options menu when you edit any .vhd ﬁle. This

will be a great help when learning VHDL and most of the default VHDL statements are present in

the menu. Note that when you write you VHDL code for the inverter the entity is called inverter

which is the same name that you used for the directory. Please name the top level entity in your

design the same as the directory that it lives in. Please look at the comments in the code below for

information about the speciﬁcs.

vhdl.vhd ﬁle for the inverter.

- -

- - Entity: inverter

- - Architecture : structural

- - Author: cpatel2

- - Created On: 10/20/00 at 13:32

- -

-- These are the standard libraries that you are deﬁning.

library IEEE;

use IEEE.std_logic_1164. all ;

-- The entity name should be same as the directory name that you are designing in.

-- Ports are the inputs and outputs from your circuit.

entity inverter is

port (

input : in std_logic ;

output : out std_logic );

end inverter ;

-- Deﬁne an architecture for the inverter entity which is either functional or behavioral.

architecture structural of inverter is

begin

-- Concurrent assignment statement.

output <= not (input);

end structural ;

Prepared by :- Chintan Patel

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CMSC 711 CADENCE TUTORIAL Dr. Jim Plusquellic

Now before we go on to compiling and simulating we need to make a test bench to test the

code that we just entered. A test bench is another VHDL ﬁle that uses your design ﬁle and gives it

inputs and checks the outputs. The input and output is done using text ﬁles through the VHDL

code using inbuilt I/O functions. For making a test bench make are directory called inverter_test

in your ~/cadence/vhdl directory. Then make a vhdl directory under the inverter_test directory the

same way as you did for the inverter. Inside the inverter_test/vhdl directory make a ﬁle called

vhdl.vhd and enter the code for you test bench in it. The test bench ﬁle is available on the course

webpage and is also shown below. Again the entity should have the same name as the directory

you are designing in. The color formatting is not shown here as in the previous case but will be

present if you use the emacs editor.

vhdl.vhd ﬁle for the test bench .

- -

- - Entity: inverter_test

- - Architecture : vhdl

- - Author: cpatel2

- - Created On: 10/20/00 at 01:55

- -

- - Deﬁne the libraries that you are going to use. The two textio libraries deﬁne your input and

- - output functions

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_textio.all;

use STD.textio.all;

- - The entity name here is also the name as the directory that you are designing in.

- - The circuit has no ports because this is a test bench ﬁle that you are using to test the inverter.

entity inverter_test is

end inverter_test;

- - Deﬁne an architecture for the inverter_test entity.

architecture test of inverter_test is

- - Deﬁne the inverter as a component that you will use in this ﬁle. The port list is the same as

- - the original port list of the inverter entity.

component inverter

port (

input : in std_logic;

output : out std_logic);

end component;

Prepared by :- Chintan Patel

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CMSC 711 CADENCE TUTORIAL Dr. Jim Plusquellic

- - Deﬁne an instance of the inverter that you are going to use in this ﬁle.

for i1 : inverter use entity work.inverter(structural);

signal ip,op : std_logic;

signal clock : std_logic;

begin

- - Assign inputs and outputs to the various inverter ports.

i1 : inverter port map (ip,op);

- - Control the inputs to the circuit.

clk : process

begin -- process clk

clock<=’0’,’1’ after 5 ns;

wait for 10 ns;

end process clk;

- - Read inputs from a input ﬁle called inverter_in.txt and write outputs to inverter_out.txt

io_process: process

ﬁle inﬁle : text is in "inverter_in.txt";

ﬁle outﬁle : text is out "inverter_out.txt";

variable ip1,op1 : std_logic;

variable buf : line;

begin

while not (endﬁle(inﬁle)) loop

readline(inﬁle,buf);

read (buf,ip1);

ip<=ip1;

wait until falling_edge(clock);

op1:=op;

write(buf,op1);

writeline(outﬁle,buf);

end loop;

wait;

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CMSC 711 CADENCE TUTORIAL Dr. Jim Plusquellic

end process io_process;

end test;

After creating the circuit ﬁle for the inverter and the test bench to test the same we are now

ready to compile and simulate the circuit. But ﬁrst we need to create the inverter_in.txt ﬁle that

speciﬁes the input sequences that will be assigned to the inputs to the circuit. This ﬁle is created in

the ~/cadence/vhdl directory. The ﬁle should have one sequence per line. In our case the

sequences will only be a single bit sequence because we have a single bit input. The

inverter_in.txt ﬁle is shown below.

inverter_in.txt ﬁle

The sequence are assigned arbitrarily. The inverter_out.txt ﬁle will be generated automatically

in the ~/cadence/vhdl directory when you simulate the circuit. As the circuit we have imple-

mented is a simple inverter the inverter_out.txt ﬁle would look like the one shown below.

inverter_out.txt ﬁle

There are three steps involved in running a simulation. First is compiling the VHDL code, then

elaborating the design and ﬁnally simulating. Thus we ﬁrst need to compile the inverter entity as

well as the test bench entity. Next we will elaborate both these entities. Now we will simulate the

test bench. It is not required to simulate the inverter as it is because it doesn’t have any inputs

applied to the circuit.

Compiling the ~/cadence/vhdl/inverter/vhdl/vhdl.vhd ﬁle.

The command for the compilation step is shown below and should be run from the ~/cadence/

vhdl directory.

ncvhdl -cdslib ~/cadence/vhdl/cds.lib -hdlvar ~/cadence/vhdl/hdl.var -messages inverter/vhdl/

vhdl.vhd.

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