lpc47m182.pdf

LPC47M182

Advanced I/O Controller with

Motherboard GLUE Logic

Datasheet

Product Features

3.3V Operation (5V tolerant)

Enhanced Digital Data Separator

− 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps

Data Rates

− Programmable Precompensation Modes

LPC Interface

− Multiplexed Command, Address and Data Bus

− Serial IRQ Interface Compatible with Serialized IRQ

Support for PCI Systems

Keyboard Controller

− 8042 Software Compatible

− 8 Bit Microcomputer

− 2k Bytes of Program ROM

− 256 Bytes of Data RAM

− Four Open Drain Outputs Dedicated for

Keyboard/Mouse Interface

− Asynchronous Access to Two Data Registers and

One Status Register

− Supports Interrupt and Polling Access

− 8 Bit Counter Timer

− Port 92 Support

− Fast Gate A20 and KRESET Outputs

ACPI 1.0b/2.0 Compliant

Programmable Wake-up Event Interface

PC99a/PC2001 Compliant

General Purpose Input/Output Pins (13)

Fan Tachometer Inputs (2)

Green and Yellow Power LEDs

ISA Plug-and-Play Compatible Register Set

Motherboard GLUE Logic

− 5V Reference Generation

− 5V Standby Reference Generation

− IDE Reset/Buffered PCI Reset Outputs

− Power OK Signal Generation

− Power Sequencing

− Power Supply Turn On Circuitry

− Resume Reset Signal Generation

− Hard Drive Front Panel LED

− Voltage Translation for DDC to VGA Monitor

− SMBus Isolation Circuitry

− CNR Dynamic Down Control

Serial Ports

− Two Full Function Serial Ports

− High Speed 16C550A Compatible UART with

Send/Receive 16-Byte FIFOs

− Supports 230k and 460k Baud

− Programmable Baud Rate Generator

− Modem Control Circuitry

− 480 Address and 15 IRQ Options

Infrared Port

− Multiprotocol Infrared Interface

− 32-Byte Data FIFO

− IrDA 1.0 Compliant

− SHARP ASK IR

− HP-SIR

− 480 Address, Up to 15 IRQ and Three DMA Options

2.88MB Super I/O Floppy Disk Controller

− Licensed CMOS 765B Floppy Disk Controller

− Software and Register Compatible with SMSC's

Proprietary 82077AA Compatible Core

− Supports One Floppy Drive

− Configurable Open Drain/Push-Pull Output Drivers

− Supports Vertical Recording Format

Multi-Mode Parallel Port with ChiProtect

− Standard Mode IBM PC/XT , PC/AT, and PS/2

Compatible Bi-directional Parallel Port

− Enhanced Parallel Port (EPP) Compatible - EPP 1.7

and EPP 1.9 (IEEE 1284 Compliant)

− IEEE 1284 Compliant Enhanced Capabilities Port

(ECP)

− ChiProtect Circuitry for Protection

− 960 Address, Up to 15 IRQ and Three DMA Options

16-Byte Data FIFO

− 100% IBM Compatibility

− Detects All Overrun and Underrun Conditions

Sophisticated Power Control Circuitry (PCC)

Including Multiple Powerdown Modes for

Reduced Power Consumption

− DMA Enable Logic

− Data Rate and Drive Control Registers

Interrupt Generating Registers

− Registers Generate IRQ1 – IRQ15 on Serial IRQ

Interface.

480 Address, Up to Eight IRQ and Three DMA

Options

XOR-Chain Board Test

128 Pin QFP Packages, 3.2 mm Footprint; green,

lead-free also available

SMSC LPC47M182

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

DATASHEET

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

ORDERING INFORMATION

Order Number(s):

LPC47M182-NR for 128 pin QFP package

LPC47M182-NW for 128 pin QFP package (green, lead-free)

80 Arkay Drive

Hauppauge, NY 11788

(631) 435-6000

FAX (631) 273-3123

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete

information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no

responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without

notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does

not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC

or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard

Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors

known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.

SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause

or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further

testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale

Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems

Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES

OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND

ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.

IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES;

OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON

CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR

NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN

ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

SMSC LPC47M182

DATASHEET

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

Table Of Contents

Chapter 1 General Description ........................................................................................................... 11

Chapter 2 Pin Layout........................................................................................................................... 12

Chapter 3 Description of Pin Functions ............................................................................................. 14

3.1 Buffer Name Descriptions ................................................................................................................. 23

3.2 Pins With Internal Resistors .............................................................................................................. 23

3.3 Pins That Require External Resistors ............................................................................................... 24

3.4 Default State of Pins.......................................................................................................................... 25

Chapter 4 Block Diagram.................................................................................................................... 29

Chapter 5 Power and Clock Functionality......................................................................................... 30

5.1 3 Volt Operation / 5 Volt Tolerance ................................................................................................... 30

5.2 VCC Power........................................................................................................................................ 30

5.3 VTR Power ........................................................................................................................................ 30

5.3.1 Trickle Power Functionality.....................................................................................................................31

5.4 V5P0_STBY Power ........................................................................................................................... 31

5.5 32.768 kHz Trickle Clock Input.......................................................................................................... 31

5.5.1 Indication of 32KHZ Clock ......................................................................................................................31

5.6 14.318 MHz Clock Input .................................................................................................................... 32

5.7 Internal PWRGOOD .......................................................................................................................... 32

5.8 Maximum Current Values.................................................................................................................. 32

5.9 Power Management Events (PME/SCI)............................................................................................ 32

Chapter 6

Functional Description....................................................................................................... 33

6.1

Super I/O Registers........................................................................................................................... 33

6.2

Host Processor Interface (LPC) ........................................................................................................ 34

6.3

LPC Interface .................................................................................................................................... 34

6.3.1

LPC Interface Signal Definition ...............................................................................................................34

6.3.2

LPC Cycles .............................................................................................................................................34

6.3.3

Field Definitions ......................................................................................................................................35

6.3.4

NLFRAME Usage ...................................................................................................................................35

6.3.5

I/O Read and Write Cycles .....................................................................................................................35

6.3.6

DMA Read and Write Cycles ..................................................................................................................35

6.3.7

DMA Protocol .........................................................................................................................................35

6.3.8

POWER MANAGEMENT .......................................................................................................................36

6.3.9

SYNC Protocol .......................................................................................................................................36

6.3.10

I/O and DMA START Fields ................................................................................................................37

6.3.11

LPC TRANSFERS ..............................................................................................................................37

6.4

Floppy Disk Controller ....................................................................................................................... 38

6.4.1

FDC Configuration Registers ..................................................................................................................38

6.4.2

FDC Internal Registers ...........................................................................................................................38

6.4.3

STATUS REGISTER A (SRA) ................................................................................................................39

6.4.4

STATUS REGISTER B (SRB) ................................................................................................................40

6.4.5

DIGITAL OUTPUT REGISTER (DOR) ...................................................................................................42

6.4.6

TAPE DRIVE REGISTER (TDR) ............................................................................................................44

6.4.7

DATA RATE SELECT REGISTER (DSR) ..............................................................................................45

6.4.8

MAIN STATUS REGISTER ....................................................................................................................47

6.4.9

DATA REGISTER (FIFO) .......................................................................................................................48

6.4.10

DIGITAL INPUT REGISTER (DIR)......................................................................................................49

6.4.11

CONFIGURATION CONTROL REGISTER (CCR) .............................................................................50

6.4.12

STATUS REGISTER ENCODING ......................................................................................................51

SMSC LPC47M182

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

DATASHEET

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

6.5 MODES OF OPERATION ................................................................................................................. 53

6.5.1 PC/AT mode ...........................................................................................................................................53

6.5.2 PS/2 mode ..............................................................................................................................................54

6.5.3 Model 30 mode .......................................................................................................................................54

6.6 DMA TRANSFERS............................................................................................................................ 54

6.7 CONTROLLER PHASES .................................................................................................................. 54

6.7.1 Command Phase ....................................................................................................................................54

6.7.2 Execution Phase.....................................................................................................................................54

6.8 Data Transfer Termination ................................................................................................................ 55

6.9 Result Phase ..................................................................................................................................... 55

6.10 Command Set/Descriptions ........................................................................................................... 56

6.10.1 Instruction Set .....................................................................................................................................59

6.11 Data Transfer Commands.............................................................................................................. 65

6.11.1 Read Data ...........................................................................................................................................65

6.12 Read Deleted Data......................................................................................................................... 66

6.13 Read A Track ................................................................................................................................. 67

6.14 Write Data ...................................................................................................................................... 68

6.15 Write Deleted Data......................................................................................................................... 68

6.16 Verify .............................................................................................................................................. 68

6.17 Format A Track .............................................................................................................................. 69

6.18 Control Commands ........................................................................................................................ 71

6.18.1 Read ID...............................................................................................................................................71

6.18.2 Recalibrate ..........................................................................................................................................71

6.18.3 Seek....................................................................................................................................................71

6.19 Sense Interrupt Status ................................................................................................................... 72

6.20 Sense Drive Status ........................................................................................................................ 73

6.21 Specify ........................................................................................................................................... 73

6.22 Configure........................................................................................................................................ 73

6.22.1 Configure Default Values: ...................................................................................................................73

6.23 Version ........................................................................................................................................... 74

6.24 Relative Seek ................................................................................................................................. 74

6.25 Perpendicular Mode ....................................................................................................................... 75

6.26 Lock................................................................................................................................................ 77

6.27 Enhanced DUMPREG.................................................................................................................... 77

6.27.1 COMPATIBILITY.................................................................................................................................77

6.28 Serial Port (UART) ......................................................................................................................... 77

6.28.1 REGISTER DESCRIPTION ................................................................................................................78

6.28.2 RECEIVE BUFFER REGISTER (RB) .................................................................................................78

6.28.3 TRANSMIT BUFFER REGISTER (TB) ...............................................................................................79

6.28.4 INTERRUPT ENABLE REGISTER (IER)............................................................................................79

6.28.5 FIFO CONTROL REGISTER (FCR) ...................................................................................................80

6.28.6 INTERRUPT IDENTIFICATION REGISTER (IIR) ...............................................................................80

6.28.7 LINE CONTROL REGISTER (LCR)....................................................................................................82

6.28.8 MODEM CONTROL REGISTER (MCR) .............................................................................................84

6.28.9 LINE STATUS REGISTER (LSR) .......................................................................................................85

6.28.10 MODEM STATUS REGISTER (MSR).................................................................................................86

6.28.11 SCRATCHPAD REGISTER (SCR) .....................................................................................................87

6.29 Programmable Baud Rate Generator (And Divisor Latches DLH, DLL)........................................ 87

6.29.1

Effect Of The Reset on Register File...................................................................................................87

6.29.2

FIFO INTERRUPT MODE OPERATION.............................................................................................88

6.29.3

FIFO POLLED MODE OPERATION ...................................................................................................88

Chapter 7

Notes On Serial Port Operation........................................................................................ 93

7.1

FIFO Mode Operation: ...................................................................................................................... 93

7.1.1

GENERAL ..............................................................................................................................................93

7.1.2

TX AND RX FIFO OPERATION .............................................................................................................93

7.2

Infrared Interface ............................................................................................................................... 94

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

SMSC LPC47M182

DATASHEET

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

7.3 Parallel Port ....................................................................................................................................... 95

7.4 IBM XT/AT Compatible, Bi-Directional and EPP Modes ................................................................... 96

7.4.1 DATA PORT ...........................................................................................................................................96

7.4.2 Status Port ..............................................................................................................................................97

7.4.3 CONTROL PORT ...................................................................................................................................97

7.4.4 EPP ADDRESS PORT ...........................................................................................................................98

7.4.5 EPP DATA PORT 0 ................................................................................................................................98

7.4.6 EPP DATA PORT 1 ................................................................................................................................99

7.4.7 EPP DATA PORT 2 ................................................................................................................................99

7.4.8 EPP DATA PORT 3 ................................................................................................................................99

7.5 EPP 1.9 Operation ............................................................................................................................ 99

7.5.1 Software Constraints ..............................................................................................................................99

7.6 EPP 1.9 Write .................................................................................................................................. 100

7.7 EPP 1.9 Read.................................................................................................................................. 100

7.8 EPP 1.7 Operation .......................................................................................................................... 101

7.8.1 Software Constraints ............................................................................................................................101

7.9 EPP 1.7 Write .................................................................................................................................. 101

7.10 EPP 1.7 Read .............................................................................................................................. 101

7.10.1 Extended Capabilities Parallel Port ...................................................................................................102

7.10.2 Vocabulary ........................................................................................................................................102

7.11 ECP Implementation Standard .................................................................................................... 103

7.11.1 Description ........................................................................................................................................103

7.12 Register Definitions ...................................................................................................................... 104

7.12.1 DATA and ecpAFifo PORT ...............................................................................................................105

7.12.2 DEVICE STATUS REGISTER (dsr) ..................................................................................................106

7.12.3 DEVICE CONTROL REGISTER (dcr)...............................................................................................106

7.12.4 CFIFO (Parallel Port Data FIFO).......................................................................................................107

7.12.5 ECPDFIFO (ECP Data FIFO)............................................................................................................107

7.12.6 tFifo (Test FIFO Mode)......................................................................................................................107

7.12.7 cnfgA (Configuration Register A).......................................................................................................108

7.12.8 cnfgB (Configuration Register B).......................................................................................................108

7.12.9 ecr (Extended Control Register)........................................................................................................108

7.13 Operation ..................................................................................................................................... 110

7.13.1 Mode Switching/Software Control .....................................................................................................110

7.14 ECP Operation ............................................................................................................................. 110

7.15 Termination from ECP Mode ....................................................................................................... 111

7.16 Command/Data ............................................................................................................................ 111

7.17 Data Compression ....................................................................................................................... 111

7.18 Pin Definition ................................................................................................................................ 112

7.19 LPC Connections ......................................................................................................................... 112

7.20 Interrupts ...................................................................................................................................... 112

7.21 FIFO Operation ............................................................................................................................ 112

7.21.1 DMA TRANSFERS ...........................................................................................................................113

7.21.2 DMA Mode - Transfers from the FIFO to the Host ............................................................................113

7.21.3 Programmed I/O Mode or Non-DMA Mode .......................................................................................113

7.21.4 Programmed I/O - Transfers from the FIFO to the Host....................................................................114

7.21.5 Programmed I/O - Transfers from the Host to the FIFO....................................................................114

7.22 Power Management ..................................................................................................................... 114

7.23 Serial IRQ..................................................................................................................................... 114

7.23.1

Timing Diagrams For SER_IRQ Cycle ..............................................................................................115

7.23.2

SER_IRQ Cycle Control....................................................................................................................115

7.23.3

SER_IRQ Data Frame ......................................................................................................................116

7.23.4

Stop Cycle Control ............................................................................................................................117

7.23.5

Latency .............................................................................................................................................117

7.23.6

EOI/ISR Read Latency......................................................................................................................117

7.23.7

AC/DC Specification Issue ................................................................................................................117

7.23.8

Reset and Initialization ......................................................................................................................117

7.24

Interrupt Generating Registers..................................................................................................... 117

SMSC LPC47M182

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

DATASHEET

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