ESD In Silicon Integrated Circuits.pdf

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2002 John Wiley & Sons, Ltd
ISB N s : 0-471-49871-8 (Hardback); 0-470-84605-4 (Electronic)
ESD in Silicon Integrated Circuits, 2nd Edition
Ajith Amerasekera, Charvaka Duvvury
Copyright c
ESD in Silicon
Integrated Circuits
Second Edition
23341910.002.png
ESD in Silicon
Integrated Circuits
Second Edition
Ajith Amerasekera
Charvaka Duvvury
Texas Instruments, Inc., USA
With
Warren Anderson
Compaq Computer Corporation, USA
Horst Gieser
Fraunhofer Institute for Reliability and
Microintegration IZM ATIS, Germany
Sridhar Ramaswamy
Texas Instruments, Inc., USA
23341910.003.png 23341910.004.png 23341910.005.png
Copyright c
2002 by John Wiley & Sons, Ltd.,
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British Library Cataloguing in Publication Data
A catalogue record for this book is available from the British Library
ISBN 0 470 49871 8
Typeset in 10/12pt Times by Laserwords Private Limited, Chennai, India.
Printed and bound in Great Britain by Antony Rowe Ltd., Chippenham, Wiltshire.
This book is printed on acid-free paper responsibly manufactured from sustainable forestry
in which at least two trees are planted for each one used for paper production.
Contents
Preface
ix
1 Introduction
1
1.1 Background
1
1.2 The ESD Problem
3
1.3 Protecting Against ESD
4
1.4 Outline of the Book
4
Bibliography
7
2 ESD Phenomenon
8
2.1 Introduction
8
2.2 Electrostatic Voltage
9
2.3 Discharge
11
2.4 ESD Stress Models
12
Bibliography
15
3 Test Methods
17
3.1 Introduction
17
3.2 Human Body Model (HBM)
18
3.3 Machine Model (MM)
27
3.4 Charged Device Model (CDM)
28
3.5 Socket Device Model (SDM)
40
3.6 Metrology, Calibration, Verification
42
3.7 Transmission Line Pulsing (TLP)
47
3.8 Failure Criteria
58
3.9 Summary
60
Bibliography
61
4 Physics and Operation of ESD Protection Circuit Elements
68
4.1 Introduction
68
4.2 Resistors
68
4.3 Diodes
70
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vi
CONTENTS
4.4 Transistor Operation
77
4.5 Transistor Operation under ESD Conditions
85
4.6 Electrothermal Effects
95
4.7 SCR Operation
98
4.8 Conclusion
101
Bibliography
102
5 ESD Protection Circuit Design Concepts and Strategy
105
5.1 The Qualities of Good ESD Protection
106
5.2 ESD Protection Design Methods
109
5.3 Selecting an ESD Strategy
123
5.4 Summary
124
Bibliography
124
6 Design and Layout Requirements
126
6.1 Introduction
126
6.2 Thick Field Device
127
6.3 nMOS Transistors (FPDs)
132
6.4 Gate-Coupled nMOS (GCNMOS)
138
6.5 Gate Driven nMOS (GDNMOS)
149
6.6 SCR Protection Device
150
6.7 ESD Protection Design Synthesis
155
6.8 Total Input Protection
164
6.9 ESD Protection Using Diode-Based Devices
172
6.10 Power Supply Clamps
176
6.11 Bipolar and BiCMOS Protection Circuits
179
6.12 Summary
183
Bibliography
184
7 Advanced Protection Design
188
7.1 Introduction
188
7.2 PNP-Driven nMOS (PDNMOS)
188
7.3 Substrate Triggered nMOS (STNMOS)
189
7.4 nMOS Triggered nMOS (NTNMOS)
192
7.5 ESD for Mixed-Voltage I/O
200
7.6 CDM Protection
214
7.7 SOI Technology
215
7.8 High-Voltage Transistors
216
7.9 BiCMOS Protection
218
7.10 RF Designs
219
7.11 General I/O Protection Schemes
220
7.12 Design/Layout Errors
221
7.13 Summary
223
Bibliography
224

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