Lenovo_B460_V460_-_WISTRON_LA46-UMA_-_REV_1.pdf

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5
4
3
2
1
USB BD
LA46 UMA Block Diagram
Thermal
Sensor
EMC210 11
PCB LAYER
Clock GEN
CK505
I/O BD
LA46-UMA-1_0104
L1: Top
3
L2: VCC
L3: Signal
D
D
Project Code: 91.4GV01.001
PCB(Raw Card): 09922-1
CRT BD
L4: Signal
UNBUFFERED
DDR3 SODIMM
Channel A
L5: GND
Intel CPU
Auburndale
(Dual Core)
DDR3 800/1066
L6: Bottom
Socket1
Power BD
12
204-PIN DDR3 SODIMM
Finger Printer BD
UNBUFFERED
DDR3 SODIMM
CPU DC/DC
Channel B
DDR3 800/1066
DDR3 800/1066MHz
ISL62882
OUTPUTS
VCC_CORE
38,39
Socket2
4,5,6,7,8,9,10
AV BD
INPUTS
DCBATOUT
13
FDI
DMI x4
BT BD
SYSTEM DC/DC
40
TPS51123
INPUTS
Intel
PCH HM55
OUTPUTS
5V_AUX_S5
3D3V_AUX_S5
DCBATOUT
5V_S5
14'' WUXGA
(WSXGA) LCD
3D3V_S5
USB 2.0 (12 ports)
LVDS
C
Mic in
24
C
HD AUDIO CODEC
ALC269Q-VB-GR
HDA Link
Serial ATA (4 ports)
PCI Express (8 ports)
SYSTEM DC/DC
RT8209E
41
RGB
CRT CONN
25
INPUTS
OUTPUTS
AC97 2.3/Azalia Interface
ACPI 2.0
Headphone out
DCBATOUT
1D5V_S3
27
LPC I/F
PCI Rev 2.3
PCI Express 1
GLAN
AR8131
Transformer
RJ45
SYSTEM DC/DC
29
RT8209E
INPUTS
41
INT. RTC
OUTPUTS
SATA HDD
SATA CONN
SATA Port 0
DCBATOUT
1D05V_S0
28
USB 2.0 CH3
14,15,16,17,18,19,20,21,22
Mini PCI-E
SYSTEM DC/DC
RT8209E
31
SATA ODD
WLAN Card
42
SATA CONN
SATA Port 4
28
PCI Express 2
INPUTS
OUTPUTS
DCBATOUT
1D05V_VTT
USB 2.0 CH5
5-in-1
Slot
MediaCard Reader
Realtek/5159
USB 2.0 CH4
Mini PCI-E
SIM Slot
LDO
31
WWAN Card
31
RT9025
43
PCI Express 3
INPUTS
OUTPUTS
3D3V_S5
1D8V_S0
B
B
Bluetooth
CH9
32
USB 2.0 CH12
LDO
RT9026
Express Card
I/O BD
43
Camera
CH15
24
31
INPUTS
OUTPUTS
PCI Express 4
0D75_S0
1D5V_S3
DDR_VREF_S3
Finger Printer 35
CH10
SYSTEM DC/DC
LPC Bus / 33MHz
44
ISL62881
USB 2.0
INPUTS
OUTPUTS
CH1
USB BD
32
KBC
LPC Debug
DCBATOUT
VCC_GFXCORE
SPI FLASH
4MB
Nuvoton NPCE781E
USB 2.0
CH2
35
32
33
33
CHARGER
BQ24745
46
USB 2.0
CH8
INPUTS
OUTPUTS
BT+
32
Multi-touch
Touchpad
Int. KB
G-Sensor
SPI Flash
128Kb
35
DCBATOUT
33
35
A
A
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
Block Diagram
Block Diagram
Block Diagram
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
LA46-UMA
LA46-UMA
LA46-UMA
1
1
1
Date:
Date:
Date:
Monday, January 18, 2010
Monday, January 18, 2010
Monday, January 18, 2010
Sheet
Sheet
Sheet
1
1
1
of
of
of
48
48
48
5
4
3
2
1
 
5
4
3
2
1
Processor Strapping
Sequence AC
PLANAR_ID[1..0]
Pin Name Strap Description Configuration (Default value for each bit is
1 unless specified otherwise)
1:
Default
Value
AD+
3D3V_AUX_S5
5V_AUX_S5
KBC GPIn
31
23
CFG[4]
Embedded
DisplayPort
Presence
Disabled - No Physical Display Port attached to
Embedded DisplayPort.
1
Planar ID Version
Planar PCB Version
PLANAR_IDn
1
0
0
0:
Enabled - An external Display Port device is
connected to the Embedded Display Port.
0
LA46_UMA- SA
SA
S5_ENABLE (KBC)
5V_S5
CFG[3]
PCI-Express Static
Lane Reversal
1:
0:
Normal Operation.
Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
1
0
1
1
LA46_UMA- SB
LA46_UMA- SC
LA46_UMA- 1
SB
D
D
3D3V_S5
>10ms
CFG[0]
PCI-Express
Configuration
Select
1:
0:
Single PCI-Express Graphics
Bifurcation enabled
1
0
SC
RSMRST#_KBC
1
1
-1
CFG[7]
Reserved -
Temporarily used
for early
Clarksfield
samples.
Clarksfield (only for early samples pre-ES1)
-
Connect to GND with 3.01K Ohm/5% resistor
Note:
Only temporary for early CFD samples
(rPGA/BGA) [For details please refer to the WW33
MoW and sighting report].
For a common motherboard design (for AUB and CFD),
the pull-down resistor should be used. Does not
impact AUB functionality.
0
can power after power switch press
LAN_PWR_ON
3D3V_LAN_S5
7,36,38
VCC_CORE
VCC_CORE
KBC_PWRBTN#
11,20,21,24,25,26,27,28,35,36,43,48
5V_S0
5V_S0
3D3V_S0
3,5,11,12,13,14,15,16,17,18,19,20,21,24,25,26,27,31,32,33,34,35,36,37,39,40,42,43
3D3V_S0
PM_PWRBTN#
5,8,12,13,36,40,42
1D05V_S0
1D5V_S3
1D5V_S3
3,14,15,16,20,21,36,40
1D05V_S0
PM_SLP_S4#
5,7,8,19,20,21,36,37,41
1D05V_VTT
1D05V_VTT
PCH Strapping
8,20,36,42
DDR_VREF_S3
1D8V_S0
1D8V_S0
1D5V_S3
DDR3_VREF_S3
12,13,42
DDR_VREF_S3
8,36,43
VCC_GFXCORE
VCC_GFXCORE
Name
Schematics Notes
PM_SLP_S3#
5V_S0
3D3V_S0
1D8V_S0
1D5V_S0
1D05V_S0
0D75V_S0
SPKR
Reboot option at power-up
Default Mode:
No Reboot Mode with TCO Disabled:
Internal weak Pull-down.
Connect to Vcc3_3 with 8.2-kȪ
- 10-kȪ weak pull-up resistor.
INIT3_3V#
Weak internal pull-down. Do not pull high.
C
C
GNT3#/
GPIO55
Default Mode:
Low (0) = Top Block Swap Mode
Internal pull-up.
(Connect to ground with 4.7-kȪ weak
pull-down resistor).
ALL_PWRGD
INTVRMEN
High (1) = Integrated VRM is enabled
Low (0) = Integrated VRM is disabled
Left both GNT0# and GNT1# floating. No pull up
required.
Boot from PCI:
Connect GNT1# to ground with 1-kȪ pull-down
resistor. Leave GNT0# Floating.
Boot from LPC:
Connect both GNT0# and GNT1# to ground with 1-kȪ
pull-down resistor.
= Configures DMI for ESI compatible operation (for servers
only. Not for mobile/desktops).
Do not pull low.
Connect to ground with 1-kȪ
pull-down resistor.
Connect to Vcc3_3 with 8.2-kȪ weak pull-up resistor.
Left floating, no pull-down required.
Connect to Vcc3_3 with 8.2-kȪ weak pull-up
resistor.
Connect to ground with 4.7-kȪ weak pull-down
resistor.
1D05V_VTT
GNT0#,
GNT1#
Default (SPI):
VTT_PWRGD
(H_VTTPWRGD -->CPU, KBC)
GFX_VR_EN
GNT2#/
GPIO53
Default - Internal pull-up.
Low (0)
VCC_GFXCORE
GPIO33
Default:
Disable ME in Manufacturing Mode:
DIS
DGPU_PWR_EN#
SPI_MOSI
Enable iTPM:
Disable iTPM:
NV_ALE
Enable Danbury:
Disable Danbury:
3D3V_S0_NV
VGA_CORE_PWR
NC_CLE
Weak internal pull-up. Do not pull low.
HAD_DOCK_EN#
/GPIO[33]
Low (0):
High (1) :
Flash Descriptor Security will be overridden.
Flash Descriptor Security will be in effect.
DGPU_PWROK
B
B
HDA_SDO
Weak internal pull-down. Do not pull high.
1D8V_S0_NV
FBVDD
1D05V_S0_NV
HDA_SYNC
Weak internal pull-down. Do not pull high.
Weak internal pull-down. Do not pull high.
Weak internal pull-up. Do not pull low.
GPIO15
GPIO8
GPIO27
Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.
>99ms
S0_PWR_GOOD
(IMVP_VR_EN)
VCC_CORE
VR_CLKEN#
CORE_PWRGD
(SYS_PWROK, PCH_PWROK)
Platform controlled
Sillicon controlled
PM_DRAM_PWRGD
H_PWRGD
PLT_RST#
A
A
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
Reference
Reference
Reference
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A2
A2
A2
LA46-UMA
LA46-UMA
LA46-UMA
1
1
1
Date:
Date:
Date:
Monday, January 18, 2010
Monday, January 18, 2010
Monday, January 18, 2010
Sheet
Sheet
Sheet
2
2
2
of
of
of
48
48
48
5
4
3
2
1
 
5
4
3
2
1
FOR CO-LAY SLG8LV595
1D5V_S0
1D5V_S0_CK505
1
2
D
D
R159
0R3J-0-U-GP
DY
-1 1229
1D05V_CK505
-1 1229
1D05V_S0
R154
0R3J-0-U-GP
3D3V_S0
3D3V_CK505
1D5V_S0_CK505
3D3V_CK505
1D05V_CK505
R165
0R0603-PAD-1-GP
1
2
R134
0R0603-PAD-1-GP
1
2
C199
C198
C174
C191
C140
C124
C137
C159
C123
C190
C125
U1
U1
4
6
TP_27M
1
TP18
TP18
15
DREFCLK#
DOT_96#
27MHZ
3D3V_CK505
3
7
TP_27MSS
1
TP19
TP19
15
DREFCLK
DOT_96
27MHZ_SS
R150
R150
C
C
14
15
CLKIN_DMI#
SRC_2#
CPU_STOP#
CPU_STOP#
CPU_STOP#
CPU_STOP#
CPU_STOP#
CPU_STOP#
CPU_STOP#
CPU_STOP#
13
16
2
1
15
CLKIN_DMI
SRC_2
CPU_STOP#
25
CK_PW RGD
1
TP31
TP31
10KR2J-3-GP
10KR2J-3-GP
CKPWRGD/PD#
REF_0/CPU_SEL
R138
R138
33R2J-2-GP
33R2J-2-GP
11
30
1
2
15
CLK_PCIE_SATA#
CLK_ICH14
15
SRC_1/SATA#
REF_0/CPU_SEL
10
15
CLK_PCIE_SATA
SRC_1/SATA
22
28
GEN_XTAL_IN
GEN_XTAL_OUT
15
CLK_CPU_BCLK#
CPU_0#
XTAL_IN
C132
SC10P50V2JN-4GP
DY
23
27
1
15
CLK_CPU_BCLK
CPU_0
XTAL_OUT
TP26
TP26
19
31
PCH_SMBDATA
12,13,15
CPU_1#
SDA
20
32
CPU_1
SCL
PCH_SMBCLK
12,13,15
1D05V_CK505
SLG8SP585VTR-GP
SLG8SP585VTR-GP
R142
2K2R2J-2-GP
R142
2K2R2J-2-GP
3D3V_CK505
DY
DY
C165
SC12P50V2JN-3GP
10KR2J-3-GP
10KR2J-3-GP
R156
REF_0/CPU_SEL
R156
B
1
2
GEN_XTAL_IN
B
FSC
0
1
X4
X-14D3181MHZ-GP
R139
10KR2J-3-GP
CK_PW RGD
133MHz
SPEED
100MHz
GEN_XTAL_OUT
1
2
(Default)
C178
SC15P50V2JN-2-GP
Q14
Q14
-1 1230
G
37
VR_CLKEN#
2N7002A-7-GP
2N7002A-7-GP
A
A
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
CLKGEN.
CLKGEN.
CLKGEN.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
LA46-UMA
LA46-UMA
LA46-UMA
1
1
1
Date:
Date:
Date:
Monday, January 18, 2010
Monday, January 18, 2010
Monday, January 18, 2010
Sheet
Sheet
Sheet
3
3
3
of
of
of
48
48
48
5
4
3
2
1
5
4
3
2
1
CPU1A
CPU1A
1 OF 9
1 OF 9
R383
R383
B26
PEG_IRCOMP_R
1
2
49D9R2F-GP
49D9R2F-GP
PEG_ICOMPI
A26
PEG_ICOMPO
R381
R381
A24
B27
16
DMI_TXN0
DMI_RX0#
PEG_RCOMPO
EXP_RBIAS
750R2F-GP
750R2F-GP
C23
A25
1
2
16
DMI_TXN1
DMI_RX1#
PEG_RBIAS
B22
16
DMI_TXN2
DMI_RX2#
A21
K35
16
DMI_TXN3
D
DMI_RX3#
PEG_RX0#
D
J34
PEG_RX1#
B24
J33
16
DMI_TXP0
DMI_RX0
PEG_RX2#
D23
G35
16
DMI_TXP1
DMI_RX1
PEG_RX3#
B23
G32
16
DMI_TXP2
DMI_RX2
PEG_RX4#
A22
F34
16
DMI_TXP3
DMI_RX3
PEG_RX5#
F31
PEG_RX6#
D24
D35
16
DMI_RXN0
DMI_TX0#
PEG_RX7#
G24
E33
16
DMI_RXN1
DMI_TX1#
PEG_RX8#
F23
C33
16
DMI_RXN2
DMI_TX2#
PEG_RX9#
H23
D32
16
DMI_RXN3
DMI_TX3#
PEG_RX10#
B32
PEG_RX11#
D25
C31
16
DMI_RXP0
DMI_TX0
PEG_RX12#
F24
B28
16
DMI_RXP1
DMI_TX1
PEG_RX13#
E23
B30
16
DMI_RXP2
DMI_TX2
PEG_RX14#
G23
A31
16
DMI_RXP3
DMI_TX3
PEG_RX15#
J35
PEG_RX0
H34
PEG_RX1
H33
PEG_RX2
E22
F35
16
FDI_TXN0
FDI_TX0#
PEG_RX3
D21
G33
16
FDI_TXN1
FDI_TX1#
PEG_RX4
D19
E34
16
FDI_TXN2
FDI_TX2#
PEG_RX5
D18
F32
16
FDI_TXN3
FDI_TX3#
PEG_RX6
G21
D34
16
FDI_TXN4
FDI_TX4#
PEG_RX7
E19
F33
16
FDI_TXN5
FDI_TX5#
PEG_RX8
F21
B33
16
FDI_TXN6
FDI_TX6#
PEG_RX9
G18
D31
16
FDI_TXN7
FDI_TX7#
PEG_RX10
A32
PEG_RX11
C30
PEG_RX12
C
C
D22
A28
16
FDI_TXP0
FDI_TX0
PEG_RX13
C21
B29
16
FDI_TXP1
FDI_TX1
PEG_RX14
D20
A30
16
FDI_TXP2
FDI_TX2
PEG_RX15
C18
16
FDI_TXP3
FDI_TX3
G22
L33
16
FDI_TXP4
FDI_TX4
PEG_TX0#
E20
M35
16
FDI_TXP5
FDI_TX5
PEG_TX1#
F20
M33
16
FDI_TXP6
FDI_TX6
PEG_TX2#
G19
M30
16
FDI_TXP7
FDI_TX7
PEG_TX3#
L31
PEG_TX4#
F17
K32
16
FDI_FSYNC0
FDI_FSYNC0
PEG_TX5#
E17
M29
FDI_FSYNC1
PEG_TX6#
16
FDI_FSYNC1
J31
PEG_TX7#
C17
K29
16
FDI_INT
FDI_INT
PEG_TX8#
H30
PEG_TX9#
F18
H29
FDI_LSYNC0
PEG_TX10#
16
FDI_LSYNC0
D17
F29
16
FDI_LSYNC1
FDI_LSYNC1
PEG_TX11#
E28
PEG_TX12#
D29
PEG_TX13#
D27
PEG_TX14#
C26
PEG_TX15#
L34
PEG_TX0
M34
PEG_TX1
M32
PEG_TX2
L30
PEG_TX3
M31
PEG_TX4
K31
PEG_TX5
M28
PEG_TX6
H31
PEG_TX7
B
K28
B
PEG_TX8
G30
PEG_TX9
G29
PEG_TX10
F28
PEG_TX11
E27
PEG_TX12
D28
PEG_TX13
C27
PEG_TX14
C25
PEG_TX15
AUBURUNF
AUBURUNF
A
A
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
CPU(1/7)-PEG / DMI /FDI
CPU(1/7)-PEG / DMI /FDI
CPU(1/7)-PEG / DMI /FDI
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
LA46-UMA
LA46-UMA
LA46-UMA
1
1
1
Date:
Date:
Date:
Monday, January 18, 2010
Monday, January 18, 2010
Monday, January 18, 2010
Sheet
Sheet
Sheet
4
4
4
of
of
of
48
48
48
5
4
3
2
1
5
4
3
2
1
CPU1B
CPU1B
2 OF 9
2 OF 9
1D05V_VTT
H_COMP3
1
2
AT23
COMP3
R377
R377
20R2F-GP
20R2F-GP
A16
BCLK_CPU_P
BCLK_CPU_N
SM_RCOMP_0
1
2
BCLK_CPU_P
19
BCLK
1
2
H_CATERR#
1
2
H_COMP2
AT24
B16
R77
R77
100R2F-L1-GP-U
100R2F-L1-GP-U
BCLK_CPU_N
19
COMP2
BCLK#
R120
R120
49D9R2F-GP
49D9R2F-GP
R378
R378
20R2F-GP
20R2F-GP
SM_RCOMP_1
1
2
PROCHOT#
H_COMP1
R78
R78
24D9R2F-L-GP
24D9R2F-L-GP
1
2
1
2
G16
AR30
COMP1
BCLK_ITP
R145
R145
68R2-GP
68R2-GP
R127
R127
49D9R2F-GP
49D9R2F-GP
AT30
SM_RCOMP_2
1
2
BCLK_ITP#
1
2
H_COMP0
AT26
R79
R79
130R2F-1-GP
130R2F-1-GP
COMP0
R379
R379
49D9R2F-GP
49D9R2F-GP
PEG_CLK_R
E16
PEG_CLK_R 15
PEG_CLK#_R 15
DPLL_REF_SSCLK
PEG_CLK
PEG_CLK#_R
D16
PEG_CLK#
TPAD14-GP
TPAD14-GP
TP20
TP20
1
SKTOCC#_R
AH24
SKTOCC#
A18
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
15
D
DPLL_REF_SSCLK
D
A17
DPLL_REF_SSCLK#
15
DPLL_REF_SSCLK#
H_CATERR#
AK14
CATERR#
DDR3_DRAMRST#_R
F6
SM_DRAMRST#
1D05V_VTT
RN19
SRN10KJ-5-GP
AT15
19
H_PECI
PECI
AL1
SM_RCOMP_0
SM_RCOMP0
AM1
SM_RCOMP_1
1
2
4
SM_RCOMP1
SM_RCOMP_2
AN1
3
SM_RCOMP2
PROCHOT#
XDP_TDO_M
1
2
AN26
37
H_PROCHOT#
PROCHOT#
R147
R147
0R0402-PAD-1-GP
0R0402-PAD-1-GP
AN15
PM_EXTTS#0_R
12
PM_EXT_TS0#
AP15
PM_EXTTS#1_R
13
PM_EXT_TS1#
R386
0R0402-PAD-1-GP
-1 0104
AK15
19,36
PM_THRMTRIP-A#
THERMTRIP#
XDP_PRDY#
TP77
TP77
TPAD14-GP
TPAD14-GP
XDP_TDI_M
AT28
1
PRDY#
XDP_PREQ#
AP27
PREQ#
3D3V_S0
AN28
XDP_TCLK
XDP_TMS
TCK
TPAD14-GP
TPAD14-GP
TP22
TP22
H_CPURST#
1
AP26
AP28
RESET_OBS#
TMS
XDP_TRST#
XDP_DBRESET#
AT27
1
2
TRST#
R143
1KR2J-1-GP
AL15
AT29
XDP_TDI
XDP_TDO
16
H_PM_SYNC
PM_SYNC
TDI
AR27
TDO
XDP_TDI_M
XDP_TDO_M
AR29
TDI_M
1
2
VCCPW RGOOD_1
AN14
AP29
19,36
H_PW RGD
VCCPWRGOOD_1
TDO_M
R376
0R0402-PAD-1-GP
XDP_DBRESET#
AN25
DBR#
C
C
VCCPW RGOOD_0
1
2
AN27
VCCPWRGOOD_0
R155
R155
0R0402-PAD-1-GP
0R0402-PAD-1-GP
1D05V_VTT
AJ22
BPM0#
DRAMPW ROK
1
2
AK13
AK22
16
PM_DRAM_PW RGD
SM_DRAMPWROK
BPM1#
R81
R81
0R0402-PAD-1-GP
0R0402-PAD-1-GP
XDP_TMS
DY
DY
AK24
1
2
BPM2#
AJ24
R384
R384
51R2J-2-GP
51R2J-2-GP
BPM3#
SC 1118
H_VTTPW RGD
AM15
AJ25
XDP_TDI
1
DY
DY
2
VTTPWRGOOD
BPM4#
R385
R385
51R2J-2-GP
51R2J-2-GP
AH22
BPM5#
XDP_PREQ#
DY
DY
AK23
1
2
BPM6#
TPAD14-GP
TPAD14-GP
TP21
TP21
1
H_PW RGD_XDP
AM26
AH23
R151
R151
51R2J-2-GP
51R2J-2-GP
TAPPWRGOOD
BPM7#
XDP_TDO
1
2
R382
R382
51R2J-2-GP
51R2J-2-GP
R375
R375
PLT_RST#_R
1
2
AL14
18,29,31,33,35
PLT_RST#
RSTIN#
1K5R2F-2-GP
1K5R2F-2-GP
DY
DY
R115
750R2F-GP
XDP_TCLK
1
2
AUBURUNF
AUBURUNF
R158
R158
51R2J-2-GP
51R2J-2-GP
XDP_TRST#
1
2
R380
R380
51R2J-2-GP
51R2J-2-GP
SC 1117
1D5V_S3
3D3V_S5
R529
10KR2J-3-GP
S3_DY
1D5V_S3
1
2
B
R66
1KR2J-1-GP
S3_DY
B
SC 1117 Change parts
C64
SCD1U10V2KX-5GP
S3_DY
R80
1K1R2F-GP
R80
1K1R2F-GP
U13
U13
SC 1117
Change parts
S3
S3
DDR3_DRAMRST#_R
S3
S3
1
2
DDR3_DRAMRST#
12,13
U13_B
1
R67
R67
0R2J-2-GP
0R2J-2-GP
B
Q8
BSS138-7-F-GP
5
VCC
2
33,41,42
VTT_PW RGD
A
CPU_VDDQ_PW RGD
CPU_VDDQ_PW RGD
CPU_VDDQ_PW RGD
CPU_VDDQ_PW RGD
DRAMPW ROK
4
1
2
Y
3
R50
R50
1K5R2F-2-GP
S3_DY
1K5R2F-2-GP
S3_DY
S
D
GND
74LVC1G08GW -1-GP
S3_DY
74LVC1G08GW -1-GP
S3_DY
R49
750R2F-GP
S3_DY
R87
3KR2F-GP
R87
3KR2F-GP
Vgs(th)<=1.5V
S3
S3
R71
100KR2J-1-GP
S3_DY
RST_GATE
19
C81
SCD1U10V2KX-5GP
S3_DY
3D3V_S5
3D3V_S0
R320
100KR2J-1-GP
R336
10KR2J-3-GP
Q29
Q29
1D05V_VTT
1
2
3
6
A
A
<Variant Name>
<Variant Name>
<Variant Name>
VTT_PW RGD
H_VTTPW RGD_R
5
33,41,42
VTT_PW RGD
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
4
R337
1KR2J-1-GP
C387
SCD1U10V2KX-5GP
DY
DMN66D0LDW -7-GP
DMN66D0LDW -7-GP
Title
Title
Title
H_VTTPW RGD
CPU(2/7)-HOST
CPU(2/7)-HOST
CPU(2/7)-HOST
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
LA46-UMA
LA46-UMA
LA46-UMA
1
1
1
Date:
Date:
Date:
Monday, January 18, 2010
Monday, January 18, 2010
Monday, January 18, 2010
Sheet
Sheet
Sheet
5
5
5
of
of
of
48
48
48
5
4
3
2
1

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