volume37-number1(1).pdf

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A forum for the exchange of circuits, systems, and software for real-world signal processing
Volume 37, Number 1, 2003
Editor’s Notes, Authors
2
Getting 14-bit Integral Linearity
from a 32-Channel 14-Bit String DAC
3
Glueless, Hot-Swappable
CompactFlash Interface
7
New iMEMS Angular
Rate-Sensing Gyroscope
12
New Products
15
 
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Editor’s Notes
Welcome to 4-12 publication
As a few of our most devout readers
are perhaps already aware, we are now
committed to a schedule that is a laid-back
equivalent of “7-24”—i.e., distributing a
print edition four times a year and hosting
an online edition updated monthly. Each
edition has its unique advantages—and
disadvantages. Fortunately, the strengths
and weaknesses of one complement the
minuses and pluses of the other. Together
they ill a multitude of needs.
Available free, the online edition 1 boasts freshness. It is here that
the articles destined to endure in this print edition irst see the light
of the CRT or lat-panel display—both as informal HTMLs with
useful hyperlinks to associated information, and as easy-to-print
dressed-up PDFs.
The online edition also features brief descriptions of timely new
products (available in quantity) and pre-release products (available
for sampling), with links to data sheets and other information on the
ADI website. Also included is “Potpourri,” a user-friendly means
to access a huge variety of current online information—both on
the ADI website and elsewhere. Potpourri includes links to “what’s
new,” Analog Dialogue archives, application notes, technical support,
patents, data sheet revisions, articles in the trade press, book reviews,
and much more. The online edition also gives you the power to
immediately feed back questions and comments.
Its main weakness is that it’s only available through an electronic
medium. And you can’t read it in hard copy unless you print it out.
The print edition, on the other hand, can be carried and read just
about anywhere, under any conditions (except darkness). It includes
the articles published during the most recent calendar quarter (and
their authors’ bios), and it lists all the products released during that
quarter. It may also include other material that we think you would
like to see. Since it’s printed on paper, you can make annotations, even
write phone numbers and recipes in blank areas. If you wish, you can
keep it for your print library—and you can trust that the contents will
not change during its lifetime (but unfortunately, the rare mistake or
typo will similarly be “cast in concrete”!).
The best news of all is that you can subscribe to both for free! Besides
getting the best of both worlds, you’ll ind one more beneit: Your
monthly visit to Analog Dialogue online will enhance your ability
to penetrate the greater ADI website from a new point of view, one
that may have even more immediacy than the design of the Analog
Devices home page 2 allows.
AUTHORS
John Geen (page 12) has been with Analog
Devices (ADI) for nine years. He graduated
with honors in Chemistry from the University
of Manchester, England, in 1968, and
subsequently earned degrees in Electrical
Engineering and Mathematics. He has spent
most of his working life designing precision
electronics and inertial sensors for Sperry
Gyroscope, British Aerospace, and Northrop.
During that time he has been granted over
20 patents. He has concentrated on MEMS
accelerometers and gyroscopes since 1988.
David Krakauer (page 12) is Program
Manager for iMEMS gyro products in ADI’s
Micromachined Products Division. Previously,
he was strategic marketing manager for mixed-
signal DSPs. Prior to joining Analog Devices,
David was a device and reliability engineer at
Digital Equipment Corporation, and was also
product development manager for Digital’s
graphics-accelerator ICs. He holds four US
patents and has authored or co-authored
more than 10 papers on solid-state physics and reliability. David
holds bachelor’s and master’s degrees in Electrical Engineering and
Computer Science from the Massachusetts Institute of Technology—
and an MBA from MIT’s Sloan School of Management.
Albert O’Grady (page 3) is a Staff Engineer
with the general-purpose digital-to-analog
converter (DAC) product line Applications
Group, in Limerick, Ireland. He works on new
product deinitions and provides product and
customer support. Albert holds a BEng from the
University of Limerick and has authored several
technical articles on high resolution A/D and D/A
converters. In his spare time, he enjoys reading
and playing badminton and tennis.
John Tomarakos (page 7) is a DSP Field
Applications Engineer for Analog Devices,
focusing on automotive digital audio and
telematics systems. He received a BSEE degree
from the University of Pittsburgh in 1992. From
1995 to 2002, he was a member of ADI’s DSP
Central Applications Team, in Norwood, MA,
supporting the ADSP-218x and ADSP-2116x
digital signal processor families.
Dan Sheingold, Editor
www.analog.com/analogdialogue dialogue.editor@analog.com
Analog Dialogue is the free technical magazine of Analog Devices, Inc., published
continuously for 37 years—starting in 1967. It discusses products, applications,
technology, and techniques for analog, digital, and mixed-signal processing. It is
currently published in two editions— on-line , monthly at the above URL, and—less
frequently— in print , as periodic retrospective collections of articles that have appeared
on-line. In addition to technical articles, the on-line edition has timely announcements,
linking to data sheets of newly released and pre-release products, and “Potpourri”—a
universe of links to important and rapidly proliferating sources of relevant information
and activity on the Analog Devices website and elsewhere. The Analog Dialogue site
is, in effect, a “high-pass-iltered” point of entry to the www.analog.com site—the
virtual world of Analog Devices . In addition to all its current information, the
Analog Dialogue site has archives with all recent editions, starting from Volume 29,
Number 2 (1995), plus three special anniversary issues, containing useful articles
extracted from earlier editions, going all the way back to Volume 1, Number 1.
If you wish to subscribe to—or receive copies of—the print edition, please go to
www.analog.com/analogdialogue and click on <subscribe> . Your comments
are always welcome; please send messages to dialogue.editor@analog.com
or to these individuals: Dan Sheingold , Editor [dan.sheingold@analog.com]
or Scott Wayne , Managing Editor and Publisher [scott.wayne@analog.com] .
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1 http://www.analog.com/analogdialogue
2 http://www.analog.com
2
ISSN 0161-3626 ©Analog Devices, Inc. 2003
Analog Dialogue Volume 37 Number 1
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Getting 14-Bit Performance
from a 32-Channel 14-Bit
String DAC
by Albert O’Grady [albert.ogrady@analog.com]
OVERVIEW
The AD5532 32-channel, 14-bit voltage output D/A converter
can be used in DAC mode (used for accessing multiple analog
representations of digital data) or Ininite Sample-and-Hold (ISHA)
mode (for storing and accessing analog representations of analog
data). The DACs have 14-bit monotonicity, but only 0.39%
integral nonlinearity. This article shows how the DACs can be
calibrated to provide 14-bit performance.
In DAC mode of operation, the AD5532’s DACs are guaranteed
monotonic to 14 bits (differential nonlinearity <1 LSB)—thus
ideally suiting them for closed-loop control applications. Accuracy ,
however, is limited by the space-saving string-DAC architecture.
The DACs’ speciied integral nonlinearity (INL) error is 0.39%
max of full scale (0.15% typical), or 64 (24.5) least signiicant bits
in a 14-bit device. We can thus say that worst-case DAC integral
linearity is comparable to that of an 8-bit device, even though it
has 14-bit resolution.
This level of worst-case performance is acceptable for many
applications, especially considering that the AD5532 can at any
time economically and compactly store and read out 32 analog
data points with 61-part per million resolution. But there are
many applications where, although this kind of performance is
essential, better accuracy is also necessary. Our purpose here is to
show a way to calibrate the AD5532 for full 14-bit performance
with a maximum of only 256 calibration coeficients (128 data
points) per DAC, using a controller and a maximum of 8,192
slots of memory. Figure 2 shows the kind of improvement that
can be obtained.
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Figure 1. AD5532 Functional block diagram.
In DAC mode, the selected DAC register is written to via the
3-wire serial interface; the analog output (VOUT) for this DAC
is then updated to relect the new contents of the DAC register.
DAC selection is accomplished via ive address bits, A0-A4. The
reference, the voltage applied to the OFFS_IN pin, and the gain
of the output ampliier combine to determine the output range
of the AD5532.
In ISHA mode, the input voltage, VIN, is sampled and converted
into a digital word. The noninverting input to the selected ( n th)
output buffer (gain and offset stage) is tied to VIN during the
acquisition period to avoid transient spurious outputs while the
n th DAC acquires the correct code, a step completed in 16 s max.
The updated DAC output then is connected to the noninverting
input of the n th output buffer and assumes control of its output
voltage. Since the channel output voltage is effectively the output
of a DAC with a ixed input, there is no droop associated with it.
As long as power is maintained to the device, the output voltage
will remain constant until this channel is addressed again.
The analog output is restricted to a range from VSS + 2 V to
VDD – 2 V because of headroom constraints in the output ampliier.
The device is operated with AVCC = 5 V 5%, DVCC = 2.7 V to
5.25 V, VSS = –4.75 V to –16.5 V, and VDD = 8 V to 16.5 V; and
it requires a stable +3-V reference on REF_IN, as well as an offset
voltage on OFFS_IN.
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Figure 2. Uncalibrated linearity error compared with
post-calibration linearity error for a 128-point calibration
of a typical AD5532 channel at 25 C.
The following describes the basic DAC architecture and a method
of calibration that can be easily implemented to achieve an INL
error level of 1 LSB.
DAC Architecture
The common string DAC is one of the oldest and simplest
DAC circuit concepts. Resistor-string DAC implementations
are inherently monotonic by design and are characterized by
simplicity, small size (per resistor), and low power consumption.
But a major drawback is that 2 N resistors are required to
implement it directly—e.g., 16,384 for 14 bits. In order to reduce
the number of resistors and die size, the AD5532 incorporates
two 128-resistor strings (7 bits)—a main string DAC for the
7 more signiicant bits, and a 7-bit sub string DAC. The basic
architecture is shown in Figure 3 (US patent 5,969,657). The
sub string DAC straddles up and down the main string, always
in parallel with one of the main string resistors.
Source: Analog Dialogue Volume 37-2, February 2003
3
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The output stage then ampliies and offsets the V DAC output
as follows:
V
SUB
STRING
(2 N/2 –1 RESISTORS)
V REF_TOP
MAIN
STRING
(2 N/2 RESISTORS)
=
Gain V
×
(
Gain
− ×
1
)
V
OUT
DAC
OFFS IN
_
R
R
VDAC
TO
AMPLIFIER
where Gain is typically 3.52 and V OFFS_IN is whatever the
user programs.
For V OFFS_IN = 0 and V REF = 3 V
V OUT (zero code) = 3.52  50 mV = 176 mV (typ)
V OUT (mid-scale) = 3.52  1.525 V = 5.368 V (typ)
V OUT (full-scale) = 3.52  3 V = 10.56 V (typ)
R
R
R
R
R
Calibration Scheme
As noted above, this calibration scheme applies to all parts in
the AD5532 family. The overall INL curve can be thought of as
128 piecewise-linear segments—corresponding to deviations in
resistance value in the upper string—which are then interpolated
linearly in the lower string. Because the small resistance
deviations in the upper resistor string—which produce signiicant
nonlinearities at the 14-bit level—will vary from channel to
channel, and part to part, there is no “typical” INL curve; each
DAC needs to be individually calibrated. The calibration scheme
outlined here generates corrections to the lower 128 codes using
an Mx + C approximation for correction values in each segment.
C is the required correction at the beginning of a segment, M is
the stored slope to the beginning of the next segment, and x is the
analog ratio corresponding to a given 7-bit code.
Thus the user can develop a calibration table by measuring the
difference, C , between the expected value and the actual value at
each of the upper 128 codes, calculating the incremental slopes
( M ), and storing both values in memory for every 128-point
interval, as shown in Figure 5. Then, during run time, determine
the segment, and thus C & M , from the upper 7 bits, compute the
interpolation value determined by the lower 7 bits, and apply the
correction to the DAC input.
V REF_BOTTOM
Figure 3. General string-DAC architecture.
Directly multiplying potentiometer-style resistive DACs suffer
nonlinearity of the step size due to the variable loading of the sub
string in parallel with the main string. But in DACs such as the
AD5532, the loading of the sub string is the same at all levels and
is treated not as a major error source, but as a characteristic of the
DAC transfer function. The sub string loading error is 1 LSB.
The AD5532 DAC, using the architecture outlined above, is made
up of a 7-bit-string main DAC (128 resistors) and a 7-bit-string
sub-DAC (127 resistors) that bridges individual resistors of the
main DAC. The integral nonlinearity error (INL) is determined by
the matching of the main-DAC resistors. The sub-DAC provides
the lower 127 codes of the transfer function. The linearity of the
sub-DAC can be approximated by piecewise-linear segments.
DAC Transfer Function
The main DACs on the AD5532 are lifted off DACGND by
typically 50 mV (by means of resistors at the bottom of the DAC).
So the bottom of a DAC is typically at 50 mV, while the top of the
DAC is typically at V REF . Figure 4 shows how the nominal DAC
transfer function is derived for a single channel.
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Figure 4. AD5532 DAC equivalent circuit.
The standard DAC transfer function that applies to the AD5532 is:
Figure 5. Using DAC segments to linearize the transfer function.
Calibrating every 128 codes—i.e., every segment, will reduce the
INL error to less than 1 LSB at the 14-bit level from the worst
case 64 LSBs for the uncalibrated DAC. If all the correction
data must be stored in less memory than 8192 words, the number
of calibration points can be reduced by increasing the calibration
interval to 256 or 512 points—but this will reduce the overall
integral linearity.
N
V
=
(
V
V
)
+
V
DAC
REF TOP
_
REF BOTTOM
_
REF BOTTOM
_
16384
where
N = DAC code value in decimal (0<N<16383)
V REF_TOP = V REF and V REF_BOTTOM = 50 mV (typ)
4
Source: Analog Dialogue Volume 37-2, February 2003
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Figure 6 is a graph of linearity error for an AD5532 DAC channel
before calibration, typically of the order of 10 bits. In all these
plots, the Y axis represents the linearity error expressed in LSBs
(1 LSB = 61 ppm), while the X axis is the 14-bit code loaded to
the DAC.
As noted above, calibration can also be implemented using a smaller
number of calibration points. The increase in linearity errors that
results from using fewer calibration points is demonstrated in
Appendix B.
Hardware Implementation
Figure 8 shows a typical hardware implementation using the
AD5532. Generally the controller writes directly to the AD5532,
providing addressing and calculating calibrated data input values
to update the relevant channels.
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Figure 8. Typical hardware implementation.
The calibration scheme requires the addition of a memory block
to store the M and C calibration data for each segment in the
DAC transfer function. Using a 128-point calibration scheme, 256
calibration coeficients need to be stored for each DAC.
Calibrating the complete AD5532 requires that 8192 coeficients
be stored. In terms of memory size, the slope coeficient ( M ) will
typically require 6 bits, and the offset coeficient ( C ) also requires
about 6 bits. The memory size required can be reduced at the
expense of accuracy, as noted above and in Appendix B.
In writing data to a speciic DAC, the controller takes the input
code and goes to the memory to pick up the relevant M and
C coeficients for the segment deined by the input code. The
controller then performs a linear interpolation to determine the
correct code to write to the DAC.
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Figure 6. AD5532 Pre-calibration linearity plot.
Figure 7 shows the nonlinearity errors on the same channel,
following the implementation of a 128-point calibration, as outlined
above. It can be seen that the INL error is now within 1 LSB.
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CONCLUSION
Using a simple interpolation scheme, it is possible to
dramatically improve the linearity performance of the AD5532
family of DAC products.
We have shown that 14-bit linearity performance can be achieved
following a 128-point calibration at 25C. Pre-calibration linearity
is typically at the 8-to-10-bit level.
All that is required to upgrade an existing AD5532 for improved
performance in a system with computing power is the ability to
generate calibration information and provide a memory block to
store the calibration coeficients.
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Figure 7. Post-calibration linearity errors after
128-point calibration.
The plots in Figures 6 and 7 are at 25C. Appendix A shows the
linearity errors at –40C and +85C following the implementation
of a 128-point calibration scheme at 25C. The worst-case errors
appear to be about twice as great as at 25C.
b
ACKNOWLEDGEMENTS
We wish to thank Donal Geraghty, Patrick Kirby, John O’Sullivan,
and Catherine Redmond for their valuable contributions.
Source: Analog Dialogue Volume 37-2, February 2003
5
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