Atmega8.pdf

Features

High-performance, Low-power AVR ® 8-bit Microcontroller

Advanced RISC Architecture

– 130 Powerful Instructions – Most Single-clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

Nonvolatile Program and Data Memories

– 8K Bytes of In-System Self-Programmable Flash

Endurance: 10,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– 512 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

– 1K Byte Internal SRAM

– Programming Lock for Software Security

Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Three PWM Channels

– 8-channel ADC in TQFP and QFN/MLF package

Eight Channels 10-bit Accuracy

– 6-channel ADC in PDIP package

Eight Channels 10-bit Accuracy

– Byte-oriented Two-wire Serial Interface

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby

I/O and Packages

– 23 Programmable I/O Lines

– 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF

Operating Voltages

– 2.7 - 5.5V (ATmega8L)

– 4.5 - 5.5V (ATmega8)

Speed Grades

– 0 - 8 MHz (ATmega8L)

– 0 - 16 MHz (ATmega8)

Power Consumption at 4 Mhz, 3V, 25 ° C

– Active: 3.6 mA

– Idle Mode: 1.0 mA

– Power-down Mode: 0.5 µA

8-bit

with 8K Bytes

In-System

Programmable

Flash

ATmega8

ATmega8L

2486QS–AVR–10/06

Pin Configurations

PDIP

(RESET) PC6

(RXD) PD0

(TXD) PD1

(INT0) PD2

(INT1) PD3

(XCK/T0) PD4

VCC

GND

(XTAL1/TOSC1) PB6

(XTAL2/TOSC2) PB7

(T1) PD5

(AIN0) PD6

(AIN1) PD7

(ICP1) PB0

PC5 (ADC5/SCL)

PC4 (ADC4/SDA)

PC3 (ADC3)

PC2 (ADC2)

PC1 (ADC1)

PC0 (ADC0)

GND

AREF

AVCC

PB5 (SCK)

PB4 (MISO)

PB3 (MOSI/OC2)

PB2 (SS/OC1B)

PB1 (OC1A)

TQFP Top View

(INT1) PD3

(XCK/T0) PD4

GND

VCC

GND

VCC

(XTAL1/TOSC1) PB6

(XTAL2/TOSC2) PB7

PC1 (ADC1)

PC0 (ADC0)

ADC7

GND

AREF

ADC6

AVCC

PB5 (SCK)

MLF Top View

(INT1) PD3

(XCK/T0) PD4

GND

VCC

GND

VCC

(XTAL1/TOSC1) PB6

(XTAL2/TOSC2) PB7

PC1 (ADC1)

PC0 (ADC0)

ADC7

GND

AREF

ADC6

AVCC

PB5 (SCK)

NOTE:

The large center pad underneath the MLF

packages is made of metal and internally

connected to GND. It should be soldered

or glued to the PCB to ensure good

mechanical stability. If the center pad is

left unconneted, the package might

loosen from the PCB.

ATmega8(L)

2486QS–AVR–10/06

ATmega8(L)

Overview

The ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC

architecture. By executing powerful instructions in a single clock cycle, the ATmega8

achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to

optimize power consumption versus processing speed.

Block Diagram

Figure 1. Block Diagram

XTAL1

RESET

PC0 - PC6

PB0 - PB7

VCC

XTAL2

PORTC DRIVERS/BUFFERS

PORTB DRIVERS/BUFFERS

GND

PORTC DIGITAL INTERFACE

PORTB DIGITAL INTERFACE

MUX &

ADC

INTERFACE

TWI

AGND

AREF

PROGRAM

COUNTER

STACK

POINTER

TIMERS/

COUNTERS

OSCILLATOR

PROGRAM

FLASH

SRAM

INTERNAL

OSCILLATOR

INSTRUCTION

GENERAL

PURPOSE

REGISTERS

WATCHDOG

TIMER

OSCILLATOR

INSTRUCTION

DECODER

MCU CTRL.

& TIMING

CONTROL

LINES

ALU

INTERRUPT

UNIT

AVR CPU

STATUS

EEPROM

PROGRAMMING

LOGIC

SPI

USART

COMP.

INTERFACE

PORTD DIGITAL INTERFACE

PORTD DRIVERS/BUFFERS

PD0 - PD7

2486QS–AVR–10/06

The AVR core combines a rich instruction set with 32 general purpose working registers.

All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing

two independent registers to be accessed in one single instruction executed in one clock

cycle. The resulting architecture is more code efficient while achieving throughputs up to

ten times faster than conventional CISC microcontrollers.

The ATmega8 provides the following features: 8K bytes of In-System Programmable

Flash with Read-While-Write capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23

general purpose I/O lines, 32 general purpose working registers, three flexible

Timer/Counters with compare modes, internal and external interrupts, a serial program-

mable USART, a byte oriented Two-wire Serial Interface, a 6-channel ADC (eight

channels in TQFP and QFN/MLF packages) with 10-bit accuracy, a programmable

Watchdog Timer with Internal Oscillator, an SPI serial port, and five software selectable

power saving modes. The Idle mode stops the CPU while allowing the SRAM,

Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-

down mode saves the register contents but freezes the Oscillator, disabling all other

chip functions until the next Interrupt or Hardware Reset. In Power-save mode, the

asynchronous timer continues to run, allowing the user to maintain a timer base while

the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and

all I/O modules except asynchronous timer and ADC, to minimize switching noise during

ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the

rest of the device is sleeping. This allows very fast start-up combined with low-power

consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology.

The Flash Program memory can be reprogrammed In-System through an SPI serial

interface, by a conventional non-volatile memory programmer, or by an On-chip boot

program running on the AVR core. The boot program can use any interface to download

the application program in the Application Flash memory. Software in the Boot Flash

Section will continue to run while the Application Flash Section is updated, providing

true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-

Programmable Flash on a monolithic chip, the Atmel ATmega8 is a powerful microcon-

troller that provides a highly-flexible and cost-effective solution to many embedded

control applications.

The ATmega8 AVR is supported with a full suite of program and system development

tools, including C compilers, macro assemblers, program debugger/simulators, In-Cir-

cuit Emulators, and evaluation kits.

Disclaimer

Typical values contained in this datasheet are based on simulations and characteriza-

tion of other AVR microcontrollers manufactured on the same process technology. Min

and Max values will be available after the device is characterized.

ATmega8(L)

2486QS–AVR–10/06

ATmega8(L)

Pin Descriptions

VCC

Digital supply voltage.

GND

Ground.

Port B (PB7..PB0)

XTAL1/XTAL2/TOSC1/TOSC2

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port B output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port B pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Depending on the clock selection fuse settings, PB6 can be used as input to the invert-

ing Oscillator amplifier and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the

inverting Oscillator amplifier.

If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as

TOSC2..1 input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.

The various special features of Port B are elaborated in “Alternate Functions of Port B”

on page 58 and “System Clock and Clock Options” on page 25.

Port C (PC5..PC0)

Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port C output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port C pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

PC6/RESET

If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electri-

cal characteristics of PC6 differ from those of the other pins of Port C.

If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on

this pin for longer than the minimum pulse length will generate a Reset, even if the clock

is not running. The minimum pulse length is given in Table 15 on page 38. Shorter

pulses are not guaranteed to generate a Reset.

The various special features of Port C are elaborated on page 61.

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port D output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port D pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega8 as listed on

page 63.

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will gener-

ate a reset, even if the clock is not running. The minimum pulse length is given in Table

15 on page 38. Shorter pulses are not guaranteed to generate a reset.

2486QS–AVR–10/06

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