AD7569.PDF

LC 2 MOS

Complete, 8-Bit Analog I/0 Systems

AD7569/AD7669

FEATURES

2 m s ADC with Track/Hold

1 m s DAC with Output Amplifier

AD7569, Single DAC Output

AD7669, Dual DAC Output

On-Chip Bandgap Reference

Fast Bus Interface

Single or Dual 5 V Supplies

AD7569 FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The AD7569/AD7669 is a complete, 8-bit, analog I/O system

on a single monolithic chip. The AD7569 contains a high speed

successive approximation ADC with 2

AD7669 FUNCTIONAL BLOCK DIAGRAM

s settling time. A temperature-compensated 1.25 V

bandgap reference provides a precision reference voltage for the

ADC and the DAC. The AD7669 is similar, but contains two

DACs with output buffer amplifiers.

A choice of analog input/output ranges is available. Using a sup-

ply voltage of +5 V, input and output ranges of zero to 1.25 V

and zero to 2.5 volts may be programmed using the RANGE in-

put pin. Using a

5 V supply, bipolar ranges of

1.25 V or

2.5 V may be programmed.

Digital interfacing is via an 8-bit I/O port and standard micro-

processor control lines. Bus interface timing is extremely fast, al-

lowing easy connection to all popular 8-bit microprocessors. A

separate start convert line controls the track/hold and ADC to

give precise control of the sampling period.

The AD7569/AD7669 is fabricated in Linear-Compatible

CMOS (LC 2 MOS), an advanced, mixed technology process

combining precision bipolar circuits with low power CMOS

logic. The AD7569 is packaged in a 24-pin, 0.3" wide “skinny”

DIP, a 24-terminal SOIC and 28-terminal PLCC and LCCC

packages. The AD7669 is available in a 28-pin, 0.6" plastic

DIP, 28-terminal SOIC and 28-terminal PLCC package.

PRODUCT HIGHLIGHTS

1. Complete Analog I/O on a Single Chip.

The AD7569/AD7669 provides everything necessary to

interface a microprocessor to the analog world. No external

components or user trims are required and the overall accu-

racy of the system is tightly specified, eliminating the need

to calculate error budgets from individual component

specifications.

2. Dynamic Specifications for DSP Users.

In addition to the traditional ADC and DAC specifications,

the AD7569/AD7669 is specified for ac parameters, includ-

ing signal-to-noise ratio, distortion and input bandwidth.

3. Fast Microprocessor Interface.

The AD7569/AD7669 has bus interface timing compatible

with all modern microprocessors, with bus access and relin-

quish times less than 75 ns and write pulse width less than

80 ns.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700

World Wide Web Site: http://www.analog.com

Fax: 617/326-8703

s conversion time, a track/

hold with 200 kHz bandwidth, a DAC and an output buffer ampli-

fier with 1

AD7569/AD7669–SPECIFICATIONS

(V DD = +5 V

5%; V SS 2 = RANGE = AGND DAC = AGND ADC = DGND = 0 V; R L = 2 k

, C L = 100 pF to AGND DAC

unless otherwise noted. All specifications T MIN to T MAX unless otherwise noted.)

AD7569

J, A Versions 3

AD7569

AD7669

K, B

AD7569

Parameter

J Version

Versions

S Version T Version Units

Conditions/Comments

STATIC PERFORMANCE

Resolution 4

Bits

Total Unadjusted Error 5

LSB typ

Relative Accuracy 5

± 1

± 1/2

± 1

± 1/2

LSB max

Differential Nonlinearity 5

± 1

± 3/4

± 1

± 3/4

LSB max

Guaranteed Monotonic

Unipolar Offset Error

DAC data is all 0s; V SS = 0 V

@ +25°C

± 2

± 1.5

± 2

± 1.5

LSB max

Typical tempco is 10 mV/°C for +1.25 V range

T MIN to T MAX

± 2.5

± 2

± 2.5

± 2

LSB max

Bipolar Zero Offset Error

DAC data is all 0s; V SS = –5 V

@ +25°C

± 2

± 1 5

± 2

± 1.5

LSB max

Typical tempco is 20 mV/°C for ± 1.25 V range

T MIN to T MAX

± 2.5

± 2

± 2.5

± 2

LSB max

Full-Scale Error 6 (AD7569 Only)

V DD = 5 V

@ +25°C

± 2

± 1

± 2

± 1

LSB max

T MIN to T MAX

± 3

± 2

± 4

± 3

LSB max

Full-Scale Error 6 (AD7669 Only)

V DD = 5 V

@ +25°C

± 3

LSB max

T MIN to T MAX

± 4.5

LSB max

DACA/DACB Full-Scale Error Match 6

(AD7669 Only)

± 2.5

LSB max

V DD = 5 V

DFull Scale/DV DD , T A = +25°C

0.5

LSB max

V OUT = 2.5 V; DV DD = ± 5%

Full Scale/

V SS , T A = +25

0.5

LSB max

V OUT = –2.5 V;

V SS =

Load Regulation at Full Scale

0.2

LSB max

R L = 2 kW to °/C

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio 5 (SNR)

dB min

V OUT = 20 kHz full-scale sine wave with f SAMPLING = 400 kHz

Total Harmonic Distortion 5 (THD)

dB max

V OUT = 20 kHz full-scale sine wave with f SAMPLING = 400 kHz

Intermodulation Distortion 5 (IMD)

dB typ

fa = 18.4 kHz, fb = 14.5 kHz with f SAMPLING = 400 kHz

ANALOG OUTPUT

Output Voltage Ranges

Unipolar

0 to +1.25/2.5

Volts

V DD = +5 V, V SS = 0 V

Bipolar

± 1.25/± 2.5

Volts

V DD = +5 V, V SS = –5 V

LOG I C I NPU T S

CS, X/B,WR, RANGE, RESET, DB0–DB7

Input Low Voltage, V INL

0.8

V max

Input High Voltage, V INH

2.4

V min

Input Leakage Current

mA max

V IN = 0 to V DD

Input Capacitance 7

pF max

DB0–DB7

Input Coding (Single Supply)

Binary

Input Coding (Dual Supply)

2s Complement

AC CHARACTERlSTICS 7

Voltage Output Settling Time

Settling time to within ± 1/2 LSB of final value

Positive Full-Scale Change

ms max

Typically 1 ms

Negative Full-Scale Change (Single Supply) 4

ms max

Typically 2 ms

Negative Full-Scale Change (Dual Supply) 2

ms max

Typically 1 ms

Digital-to-Analog Glitch Impulse 5

nV secs typ

Digital Feedthrough 5

nV secs typ

V IN to V OUT Isolation

dB typ

V IN = ± 2.5 V, 50 kHz Sine Wave

DAC to DAC Crosstalk 5 (AD7669 Only)

nV secs typ

DACA to DACB Isolation 5 (AD7669 Only)

–70

dB max

POWER REQUIREMENTS

V DD Range

4.75/5.25

V min/V max For Specified Performance

V SS Range (Dual Supplies)

–4.75/–5.25

–4.75/–5.25 –4.75/–5.25 –4.75/–5.25 V min/V max Specified Performance also applies to V SS = 0 V

for unipolar ranges.

I DD

V OUT = V IN = 2.5 V; Logic Inputs = 2.4 V; CLK = 0.8 V

(AD7569)

mA max

Output unloaded

(AD7669)

mA max

Outputs unloaded

I SS (Dual Supplies)

V OUT = V IN = –2.5 V; Logic Inputs = 2.4 V; CLK = 0.8 V

(AD7569)

mA max

Output unloaded

(AD7669)

mA max

Outputs unloaded

DAC/ADC MATCHING

Gain Matching 6

V IN to V OUT match with V IN = ± 2.5 V,

@ +25°C

% typ

20 kHz sine wave

T MIN to T MAX

% typ

NOTES

1 Specifications apply to both DACs in the AD7669. V OUT applies to both V OUT A and V OUT B of the AD7669.

2 Except where noted, specifications apply for all output ranges including bipolar ranges with dual supply operation.

3 Temperature ranges as follows: J, K versions; 0°C to +70°C

A, B versions; –40°C to +85°C

S, T versions; –55°C to +125°C

4 1 LSB = 4.88 mV for 0 V to +1.25 V output range, 9.76 mV for 0 V to +2.5 V and ± 1.25 V ranges and 19.5 mV for ± 2.5 V range.

5 See Terminology.

6 Includes internal voltage reference error and is calculated after offset error has been adjusted out. Ideal unipolar full-scale voltage is (FS – 1 LSB); ideal bipolar positive full-scale voltage is (FS/2 – 1 LSB)

and ideal bipolar negative full-scale voltage is –FS/2.

7 Sample tested at +25°C to ensure compliance.

Specifications subject to change without notice.

–2–

REV. B

DAC SPECIFICATIONS 1

AD7569/AD7669

5%; V SS 1 = RANGE = AGND DAC = AGND DAC = DGND = 0 V; f CLK = 5 MHz external unless other-

wise noted. All specifications T MIN to T MAX unless otherwise noted.) Specifications apply to Mode 1 interface.

(V DD = +5 V

AD7569

J, A Versions 3

AD7569

AD7669

K, B

AD7569

Parameter

J Version

Versions

S Version

T Version

Units

Conditions/Comments

DC ACCURACY

Resolution 3

Bits

Total Unadjusted Error 4

LSB typ

Relative Accuracy 4

1/2

LSB max

Differential Nonlinearity 4

3/4

LSB max

No Missing Codes

Unipolar Offset Error

Typical tempco is 10

C for +1.25 V range; V SS = 0 V

@ +25

1.5

LSB max

T MIN to T MAX

2.5

LSB max

Bipolar Zero Offset Error

Typical tempco is 20

C for + 1.25 V range; V SS = –5 V

@ +25°C

± 3

± 2.5

± 3

± 2.5

LSB max

T MIN to T MAX

± 3.5

± 3

± 4

± 3.5

LSB max

Full-Scale Error 5

V DD = 5 V

@ +25

–4, +0

LSB max

T MIN to T MAX

–5.5, +1.5

–5.5, +1.5 –7.5, +2

–7.5, +2

LSB max

Full Scale/

V DD , T A = +25

0.5

LSB max

V IN = +2.5 V;

V DD =

Full Scale/

V SS , T A = +25

0.5

LSB max

V IN = –2.5 V;

V SS =

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio 4 (SNR)

dB min

V IN = 100 kHz full-scale sine wave with f SAMPLING = 400 kHz 6

Total Harmonic Distortion 4 (THD)

dB max

V IN = 100 kHz full-scale sine wave with f SAMPLING = 400 kHz 6

Intermodulation Distortion 4 (IMD)

dB typ

fa = 99 kHz, fb = 96.7 kHz with f SAMPLING = 400 kHz

Frequency Response

0.1

dB typ

V IN = ± 2.5 V, dc to 200 kHz sine wave

Track/Hold Acquisition Time 7

200

300

ns typ

ANALOG INPUT

Input Voltage Ranges

Unipolar

0 to +1.25/ +2.5

Volts

V DD = +5 V; V SS = 0 V

Bipolar

1.25/

2.5

Volts

V DD = +5 V; V SS = –5 V

Input Current

300

A max

See equivalent circuit Figure 5

Input Capacitance

pF typ

LOG I C I N PU T S

CS, RD, ST, CLK, RESET, RANGE

Input Low Voltage, V INL

0.8

V max

Input High Voltage, V INH

2.4

V min

I n put C ap a citance 8

pF max

CS, RD, ST, RANGE, RESET

Input Leakage Current

mA max

V IN = 0 to V DD

CLK

Input Current

I INL

–1.6

mA max

V IN = 0 V

I INH

A max

V IN = V DD

LOGIC OUTPUT S

DB0–DB7, INT, BUSY

V OL , Output Low Voltage

0.4

V max

I SINK = 1.6 mA

V OH , Output High Voltage

4.0

V min

I SOURCE = 200

DB0–DB7

Floating State Leakage Current

A max

Floating State Output Capacitance 8

pF max

Output Coding (Single Supply)

Binary

Output Coding (Dual Supply)

2s Complement

CONVERSION TIME

With External Clock

s max

f CLK = 5 MHz

With Internal Clock, T A = +25

1.6

s min

Using recommended clock components shown in Figure 21.

2.6

s max

Clock frequency can be adjusted by varying R CLK .

POWER REQUIREMENTS

As per DAC Specifications

NOTES

1 Except where noted, specifications apply for all ranges including bipolar ranges with dual supply operation.

2 Temperature ranges are as follows: J, K versions; 0

C to +70

A, B versions; –40

C to +85

3 1 LSB = 4.88 mV for 0 V to +1.25 V range, 9.76 mV for 0 V to +2.5 V and

S, T versions; –55

C to +125

1.25 V ranges and 19.5 mV for +2.5 V range.

4 See Terminology.

5 Includes internal voltage reference error and is calculated after offset error has been adjusted out. Ideal unipolar last code transition occurs at (FS – 3/2 LSB). Ideal bipolar last code transition occurs at

(FS/2 – 3/2 LSB).

6 Exact frequencies are 1 01 kHz and 384 k H z to avoid harmonics coinciding with sampling frequency.

7 Rising edge of BUSY to falling edge of ST. The time given refers to the acquisition time, which gives a 3 dB degradation in SNR from the tested figure.

8 Sample tested at +25

C to ensure compliance.

Specifications subject to change without notice.

REV. B

–3–

ADC SPECIFICATIONS

AD7569/AD7669–TIMING CHARACTERISTICS 1

Limit at

(See Figures 8, 10, 12; V DD = 5 V

5%; V SS = 0 V or –5 V

5%)

Limit at

T MIN , T MAX

Parameter

25 8 C (All Grades)

(J, K, A, B Grades)

(S, T Grades)

Units

Test Conditions/Comments

DAC Timing

t 1

ns min

W R P u lse Widt h

t 2

ns min

CS , A / B to WR Setup Time

t 3

ns min

CS, A/B to WR H o ld Time

t 4

ns min

Data Valid to WR Setup Time

t 5

ns min

Data Valid to WR Hold Time

ADC Timing

t 6

ns min

ST Pulse Wi d th

t 7

110

130

150

ns max ST to B USY Delay

t 8

ns max BUSY to IN T Delay

t 9

ns min

BU S Y to C S Delay

t 10

ns min

CS t o RD Setup Time

t 11

ns min

RD Pulse Width Determined by t 13 .

t 12

ns min

CS to RD Hold Time

t 13 2

ns max Data Access Time after RD ; C L = 20 pF

120

135

ns max Data Access Time after RD; C L = 100 pF

t 14 3

ns min

Bus Relinquish Time after RD

ns max

t 15

ns max RD to INT Delay

t 16

120

140

160

ns max RD to BUSY Delay

t 17 2

ns max Data Valid Time after BUSY ; C L = 20 pF

115

135

ns max Data Valid Time after BUSY; C L = 100 pF

NOTES

1 Sample tested at +25°C to ensure compliance. All input control signals are specified with t R = t F = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.

2 t 13 and t 17 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross either 0.8 V or 2.4 V.

3 t l4 is defined as the time required for the data line to change 0.5 V when loaded with the circuit of Figure 2.

Specifications subject to change without notice.

a. High-Z to V OH

b. High-Z to V OL

a. V OH to High-Z

b. V OL to High-Z

Figure 1. Load Circuits for Data Access Time Test

Figure 2. Load Circuits for Bus Relinquish Time Test

ABSOLUTE MAXIMUM RATINGS

V DD to AGND DAC or AGND ADC . . . . . . . . . . . . . –0.3 V, +7 V

V DD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V

V DD to V SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +14 V

AGND DAC or AGND ADC to DGND . . . . –0.3 V, V DD + 0.3 V

AGND DAC to AGND ADC . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 V

Logic Voltage to DGND . . . . . . . . . . . . . –0.3 V, V DD + 0.3 V

CLK Input Voltage to DGND . . . . . . . . . –0.3 V, V DD + 0.3 V

V OUT (V OUT A, V OUT B) to

AGND 1 DAC . . . . . . . . . . . . . . . . . V SS – 0.3 V, V DD + 0.3 V

V IN to AGND ADC . . . . . . . . . . . . . . . V SS – 0.3 V, V DD + 0.3 V

NOTE

1 Output may be shorted to any voltage in the range V SS to V DD provided that the

power dissipation of the package is not exceeded. Typical short circuit current for

a short to AGND or V SS is 50 mA.

Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW

Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C

Operating Temperature Range

Commercial (J, K) . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial (A, B) . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Extended (S, T) . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only; functional operation

of the device at these or any other condition above those indicated in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD7569/AD7669 features proprietary ESD protection circuitry, permanent dam-

age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper

ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. B

AD7569/AD7669

NOTE:

The term DAC (Digital-to-Analog Converter) throughout the

data sheet applies equally to the dual DACs in the AD7669 as

well as to the single DAC of the AD7569 unless otherwise

stated. It follows that the term V OUT applies to both V OUT A and

V OUT B of the AD7669 also.

TERMINOLOGY

Total Unadjusted Error

Total unadjusted error is a comprehensive specification that in-

cludes internal voltage reference error, relative accuracy, gain

and offset errors.

Relative Accuracy (DAC)

Relative Accuracy or endpoint nonlinearity is a measure of the

maximum deviation from a straight line passing through the

endpoints of the DAC transfer function. It is measured after al-

lowing for offset and gain errors. For the bipolar output ranges,

the endpoints of the DAC transfer function are defined as those

voltages that correspond to negative full-scale and positive full-

scale codes. For the unipolar output ranges, the endpoints are

code 1 and code 255. Code 1 is chosen because the amplifier is

now working in single supply and, in cases where the true offset

of the amplifier is negative, it cannot be seen at code 0. If the

relative accuracy were calculated between code 0 and code 255,

the “negative offset” would appear as a linearity error. If the off-

set is negative and less than 1 LSB, it will appear at code 1, and

hence the true linearity of the converter is seen between code 1

and code 255.

Relative Accuracy (ADC)

Relative Accuracy is the deviation of the ADC’s actual code

transition points from a straight line drawn between the end-

points of the ADC transfer function. For the bipolar input

ranges, these points are the measured, negative, full-scale transi-

tion point and the measured, positive, full-scale transition point.

For the unipolar ranges, the straight line is drawn between the

measured first LSB transition point and the measured full-scale

transition point.

Differential Nonlinearity

Differential Nonlinearity is the difference between the measured

change and an ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of ± 1 LSB max en-

sures monotonicity (DAC) or no missed codes (ADC). A differ-

ential nonlinearity of ± 3/4 LSB max ensures that the minimum

step size (DAC) or code width (ADC) is 1/4 LSB, and the maxi-

mum step size or code width is 3/4 LSB.

Digital-to-Analog Glitch Impulse

Digital-to-Analog Glitch Impulse is the impulse injected into the

analog output when the digital inputs change state with the

DAC selected. It is normally specified as the area of the glitch in

nV secs and is measured when the digital input code is changed

by 1 LSB at the major carry transition.

Digital Feedthrough

Digital Feedthrough is also a measure of the impulse injected to

the analog output from the digital inputs, but is measured when

the DAC is not selected. It is essentially feedthrough across the

die and package. It is also a measure of the glitch impulse trans-

ferred to the analog output when data is read from the in t ernal

ADC. It is specified in nV secs and is measured with WR high

and a digital code change from all 0s to all 1s.

DAC-to-DAC Crosstalk (AD7669 Only)

The glitch energy transferred to the output of one DAC due to

an update at the output of the second DAC. The figure given is

the worst case and is expressed in nV secs. It is measured with

an update voltage of full scale.

DAC-to-DAC Isolation (AD7669 Only)

DAC-to-DAC Isolation is the proportion of a digitized sine

wave from the output of one DAC, which appears at the output

of the second DAC (loaded with all 1s). The figure given is the

worst case for the second DAC output and is expressed as a ra-

tio in dBs. It is measured with a digitized sine wave (f SAMPLING =

100 kHz) of 20 kHz at 2.5 V pk-pk.

Signal-to-Noise Ratio

Signal-to-Noise Ratio (SNR) is the measured signal to noise at

the output of the converter. The signal is the rms magnitude of

the fundamental. Noise is the rms sum of all the nonfundamen-

tal signals (excluding dc) up to half the sampling frequency.

SNR is dependent on the number of quantization levels used in

the digitization process; the more levels, the smaller the quanti-

zation noise. The theoretical SNR for a sine wave is given by

SNR = (6.02 N + 1.76) dB

where N is the number of bits. Thus for an ideal 8-bit converter,

SNR = 50 dB.

Harmonic Distortion

Harmonic Distortion is the ratio of the rms sum of harmonics to

the fundamental. For the AD7569/AD7669, Total Harmonic

Distortion (THD) is defined as

20 log

V 2 2

+ V 3 2

+ V 4 2

+ V 5 2

+ V 6 2

V 1

where V 1 is the rms amplitude of the fundamental and V 2 , V 3 ,

V 4 , V 5 and V 6 are the rms amplitudes of the individual

harmonics.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products, of order (m + n), at sum and difference frequencies of

mfa

nfb where m, n = 0, l, 2, 3,… . Intermodulation terms

are those for which m or n is not equal to zero. For example,

the second order terms include (fa + fb) and (fa – fb) and the

third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and

(fa – 2fb).

REV. B

–5–

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