8741.PDF

8742

UNIVERSAL PERIPHERAL INTERFACE

8-BIT SLAVE MICROCONTROLLER

Y 8742: 12 MHz

Y Pin, Software and Architecturally

Compatible with 8741A

Y 8-Bit CPU plus ROM, RAM, I/O, Timer

and Clock in a Single Package

Y 2048x8EPROM,128x8RAM, 8-Bit

Timer/Counter, 18 Programmable I/O

Pins

Y One 8-Bit Status and Two Data

Registers for Asynchronous Slave-to-

Master Interface

Y DMA, Interrupt, or Polled Operation

Supported

Y Fully Compatible with all Intel and Most

Other Microprocessor Families

Y Expandable I/O

Y RAM Power-Down Capability

Y Over 90 Instructions: 70% Single Byte

Y Available in EXPRESS

Ð Standard Temperature Range

The Intel 8742 is a general-purpose Universal Peripheral Interface that allows designers to grow their own

customized solution for peripheral device control. It contains a low-cost microcomputer with 2K of program

memory, 128 bytes of data memory, 8-bit timer/counter, and clock generator in a single 40-pin package.

Interface registers are included to enable the UPI device to function as a peripheral controller in the MCS É -48,

MCS-51, MCS-80, MCS-85, 8088, 8086 and other 8-, 16-bit systems.

The 8742 is software, pin, and architecturally compatible with the 8741A. The 8742 doubles the on-chip

memory space to allow for additional features and performance to be incorporated in upgraded 8741A de-

signs. For new designs, the additional memory and performance of the 8742 extends the UPI concept to more

complex motor control tasks, 80-column printers and process control applications as examples.

290256±2

Figure 1. Pin Configuration

November 1991

Order Number: 290256-001

8742

290256±1

Figure 2. Block Diagram

8742

Table 1. Pin Description

DIP

Symbol Pin Type

Name and Function

No.

TEST 0,

I TEST INPUTS: Input pins which can be directly tested using conditional branch

instructions.

TEST 1

FREQUENCY REFERENCE: TEST 1 (T 1 ) also functions as the event timer input (under

software control). TEST 0 (T 0 ) is used during PROM programming and EPROM

verification.

XTAL 1,

INPUTS: Inputs for a crystal, LC or an external timing signal to determine the internal

oscillator frequency.

XTAL 2

RESET

I RESET : Input used to reset status flip-flops and to set the program counter to zero.

RESET is also used during EPROM programming and verification.

I SINGLE STEP: Single step input used in conjunction with the SYNC output to step the

program through each instruction (EPROM). This should be tied to a 5V when not used.

I CHIP SELECT: Chip select input used to select one UPI microcomputer out of several

connected to a common data bus.

I EXTERNAL ACCESS: External access input which allows emulation, testing and EPROM

verification. This pin should be tied low if unused.

I READ: I/O read input which enables the master CPU to read data and status words from

the OUTPUT DATA BUS BUFFER or status register.

A 0

I COMMAND/DATA SELECT: Address Input used by the master processor to indicate

whether byte transfer is data (A 0 e 0, F1 is reset) or command (A 0 e 1, F1 is set). A 0 e 0

during program and verify operations.

I WRITE: I/O write input which enables the master CPU to write data and command words

to the UPI INPUT DATA BUS BUFFER.

SYNC

11 O OUTPUT CLOCK: Output signal which occurs once per UPI instruction cycle. SYNC can

be used as a strobe for external circuitry; it is also used to synchronize single step

operation.

D 0 ±D 7 12±19 I/O DATA BUS: Three-state, bidirectional DATA BUS BUFFER lines used to interface the UPI

microcomputer to an 8-bit master system data bus.

P 10 ±P 17 27±34 I/O PORT 1: 8-bit, PORT 1 quasi-bidirectional I/O lines.

P 20 ±P 27 21±24 I/O PORT 2: 8-bit, PORT 2 quasi-bidirectional I/O lines. The lower 4 bits (P 20 ±P 23 ) interface

directly to the 8243 I/O expander device and contain address and data information during

35±38

PORT 4±7 access. The upper 4 bits (P 24 ±P 27 ) can be programmed to provide interrupt

Request and DMA Handshake capability. Software con trol can configure P 24 as Output

Buffer Full (OBF) interrupt, P 25 as Input Buffer Full (IBF) interrupt, P 26 as DMA Request

(DRQ), and P 27 as DMA ACKnowledge (DACK).

PROG 25

I/O PROGRAM: Multifunction pin used as the program pulse input during PROM programming.

During I/O expander access the PROG pin acts as an address/data strobe to the 8243.

This pin should be tied high if unused.

V CC

POWER: a 5V main power supply pin.

V DD

POWER: a 5V during normal operation. a 21V during programming operation. Low power

standby supply pin.

V SS

GROUND: Circuit ground potential.

(BUS)

8742

UPI-42 FEATURES

1. Two Data Bus Buffers, one for input and one for

output. This allows a much cleaner Master/Slave

protocol.

the IBF Status Bit. A ``0'' written to P 25 disables

the IBF pin (the pin remains low). This pin can be

used to indicate that the UPI is ready for data.

290256±5

Data Bus Buffer Interrupt Capability

290256±3

EN FLAGS Op Code: 0F5H

11110101

7 0

5. P 26 and P 27 are port pins or DMA handshake pins

for use with a DMA controller. These pins default

to port pins on Reset.

If the ``EN DMA'' instruction has been executed,

P 26 becomes the DRQ (DMA Request) pin. A ``1''

written to P 26 causes a DMA request (DRQ is acti-

vated). DRQ is deactivated by DACK # RD,

DACK # WR, or execution of the ``EN DMA'' in-

struction.

If `` EN D MA'' has been executed, P 27 becomes

the DACK (DMA Acknowledge) pin. This pin acts

as a chip select input for the Data Bus Buffer reg-

isters during DMA transfers.

2. 8 Bits of Status

ST 7 ST 6 ST 5 ST 4 F 1 F 0 IBF OBF

D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

ST 4 ±ST 7 are user definable status bits. These

bits are defined by the ``MOV STS, A'' single byte,

single cycle instruction. Bits 4±7 of the acccumu-

lator are moved to bits 4±7 of the status register.

Bits 0±3 of the status register are not affected.

MOV STS, A Op Code: 90H

10010000

7 0

3. RD and WR are edge triggered. IBF, OBF, F 1 and

IN T ch ange internally after the trailing edge of RD

or WR.

290256±4

During the time that the host CPU is reading the

status register, the 8742 is prevented from updat-

ing this register or is ``locked out''.

4. P 24 and P 25 are port pins or Buffer Flag pins

which can be used to interrupt a master proces-

sor. These pins default to port pins on Reset.

If the ``EN FLAGS'' instruction has been execut-

ed, P 24 becomes the OBF (Output Buffer Full) pin.

A ``1'' written to P 24 enables the OBF pin (the pin

outputs the OBF Status Bit). A ``0'' written to P 24

disables the OBF pin (the pin remains low). This

pin can be used to indicate that valid data is avail-

able from the UPI-41A (in Output Data Bus Buff-

er).

If `` EN F LAGS'' has been executed, P 25 becomes

the IBF (Inp ut B uffer Full) pin. A ``1'' written to P 25

enables the IBF pin (the pin outputs the inverse of

290256±6

DMA Handshake Capability

EN DMA Op Code: 0E5H

11100101

7 0

6. The RESET input on the 8742, includes a 2-stage

synchronizer to support reliable reset operation

for 12 MHz operation.

7. When EA is enabled on the 8742, the program

counter is placed on Port 1 and the lower three

bits of Port 2 (MSB e P 22 , LSB e P 10 ). On the

8742 this information is multiplexed with PORT

DATA (see port timing diagrams at end of this

data sheet).

8742

APPLICATIONS

290256±7

290256±8

Figure 3. 8088-8742 Interface

Figure 4. 8048H-8742 Interface

290256±9

290256±10

Figure 5. 8742-8243 Keyboard Scanner

Figure 6. 8742 80-Column

Matrix Printer Interface

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