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INTEGRATED CIRCUITS
80C451/83C451/87C451
CMOS single-chip 8-bit microcontrollers
Product specification
1996 Aug 16
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Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C451/83C451/87C451
DESCRIPTION
The Philips 8XC451 is an I/O expanded single-chip microcontroller
fabricated with Philips high-density CMOS technology. Philips
epitaxial substrate minimizes latch-up sensitivity.
The 8XC451 (includes the 80C451, 87C451 and 83C451) is a
functional extension of the 87C51 microcontroller with three
additional I/O ports and four I/O control lines for a total of 68 pins.
Four control lines associated with port 6 facilitate high-speed
asynchronous I/O functions.
The 8XC451 includes a 4k
PIN CONFIGURATION
9
1
61
10
60
LCC
26
44
×
8 ROM (83C451) EPROM (87C451), a
8 RAM, 56 I/O, two 16-bit timer/counters, a five source, two
priority level, nested interrupt structure, a serial I/O port for either a
full duplex UART, I/O expansion, or multi-processor
communications, and on-chip oscillator and clock circuits. The
80C451 ROMless version includes all of the 83C451 features except
the on-board 4k
×
27
43
Pin Fun ction
1 /V PP
2
Pin
Function
Pin
Function
24
P4.2
47
P5.3
P2.0/A8
25
P4.1
48
P5.4
8 ROM.
The 87C451 has 4k of EPROM on-chip as program memory and is
otherwise identical to the 83C451.
The 8XC451 has two software selectable modes of reduced activity
for further power reduction; idle mode and power-down mode. Idle
mode freezes the CPU while allowing the RAM, timers, serial port,
and interrupt system to continue functioning. Power-down mode
freezes the oscillator, causing all other chip functions to be
inoperative while maintaining the RAM contents.
×
3
P2.1/A9
26
P4.0
49
P5.5
4
P2.2/A10
27
P1.0
50
P5.6
5
P2.3/A11
28
P1.1
51
P5.7
6
P2.4/A12
29
P1.2
52
XTAL2
7
P2.5/A13
30
P1.3
53
XTAL1
8
P2.6/A14
31
P1.4
54
V SS
9
P2.7/A15
32
P1.5
55
ODS
10
P0.7/AD7
33
P1.6
56
IDS
11
P0.6/AD6
34
P1.7
57
BFLAG
12
P0.5/AD5
35
RST
58
AFLAG
13
P0.4/AD4
36
P3.0/RxD
59
P6.0
14
P0.3/AD3
37
P3.1/ TxD
60
P6.1
15
P0.2/AD2
38
P3.2/ INT0
61
P6.2
16
P0.1/AD1
39
P3.3/INT1
62
P6.3
FEATURES
•
17
P0.0/AD0
40
P3.4/T0
63
P6.4
80C51 based architecture
18
V CC
41
P3.5/ T1
64
P6.5
19
P4.7
42
P3.6/ WR
65
P6.6
•
Seven 8-bit I/O ports
20
P4.6
43
P3.7/RD
66
P6.7
21
P4.5
44
P5.0
67
PSEN
•
Port 6 features:
– Eight data pins
– Four control pins
– Direct MPU bus interface
– Parallel printer interface
22
P4.4
45
P5.1
68
ALE/PROG
23
P4.3
46
P5.2
SU00084A
•
On the microcontroller:
– 4k
8 ROM (83C451)
8 EPROM (87C451)
ROMless version (80C451)
– 128 × 8 RAM
– Two 16-bit counter/timers
– Two external interrupts
4k
×
•
External memory addressing capability
– 64k ROM and 64k RAM
•
Low power consumption:
– Normal operation: less than 24mA at 5V, 12MHz
– Idle mode
– Power-down mode
1996 Aug 16
2
853–0830 17194
128
×
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Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C451/83C451/87C451
ORDERING INFORMATION
ROMless
ROM
EPROM 1
TEMPERATURE RANGE ° C
AND PACKAGE
FREQ
MHz
DRAWING
NUMBER
SC80C451CCA68 SC83C451CCA68 SC87C451CCA68 OTP
0 to +70, Plastic Leaded Chip Carrier,
3.5 to 12 SOT188-3
SC80C451CGA68 SC83C451CGA68 SC87C451CGA68 OTP
0 to +70, Plastic Leaded Chip Carrier
3.5 to 16 SOT188-3
SC80C451ACA68 SC83C451ACA68 SC87C451ACA68 OTP –40 to +85, Plastic Leaded Chip Carrier
3.5 to 12 SOT188-3
SC80C451AGA68 SC83C451AGA68 SC87C451AGA68 OTP –40 to +85, Plastic Leaded Chip Carrier
3.5 to 16 SOT188-3
SC87C451CGK68 OTP
0 to +70, Ceramic Leaded Chip Carrier
3.5 to 16
1473A
NOTE:
1. OTP = One Time Programmable
LOGIC SYMBOL
V CC
V S S
XTAL1
A DDRESS AND
DATA BUS
XTAL2
RST
E A/V PP
PSEN
ALE/PROG
RxD
TxD
INT0
INT1
T0
T1
WR
RD
ADDRESS BUS
PORT 6 CONTROL
O DS
IDS
BFLAG
AFLAG
SU00085
1996 Aug 16
3
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Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C451/83C451/87C451
BLOCK DIAGRAM
P0.0–P0.7
P2.0–P2.7
P4.0–P4.7
P5.0–5.7
PORT 0
DRIVERS
PORT 2
DRIVERS
PORT 4
DRIVERS
PORT 5
DRIVERS
V CC
V SS
RAM ADDR
REGISTER
RAM
PORT 0
LATCH
PORT 2
LATCH
PORT 4
LATCH
PORT 5
LATCH
4K x 8
ROM/EPROM
REGISTER
B
ACC
STACK
POINTER
TMP2
TMP1
PROGRAM
ADDRESS
REGISTER
BUFFER
ALU
PCON SCON TMOD TCON
TH0
TL0
TH1
TL1
SBUF
IE
IP
PC
INCRE-
MENTER
PSW
INTERRUPT, SERIAL
PORT AND TIMER BLOCKS
PROGRAM
COUNTER
PSEN
ALE/PROG
TIMING
AND
CONTROL
DPTR
EAV PP
RST
PD
PORT 1
LATCH
PORT 6
LATCH
PORT 3
LATCH
OSCILLATOR
PORT 1
DRIVERS
PORT 6
DRIVERS
PORT 6
CONTROL/STATUS
PORT 3
DRIVERS
XTAL1
XTAL2
P1.0–P1.7
P6.0–P6.7
IDS ODS
AFLAG
BFLAG
P3.0–P3.7
SU00086
1996 Aug 16
4
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Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C451/83C451/87C451
PIN DESCRIPTION
MNEMONIC
PIN
NO.
TYPE NAME AND FUNCTION
V SS
54
I
Ground: 0V reference.
V CC
18
I
Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
P0.0–0.7
17-10
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 is also the multiplexed data and low-order
address bus during accesses to external memory. External pull-ups are required during program
verification. Port 0 can sink/source eight LS TTL inputs.
P1.0–P1.7
27-34
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 receives the low-order
address bytes during program memory verification. Port 1 can sink/source three LS TTL inputs, and
drive CMOS inputs without external pull-ups.
P2.0–P2.7
2-9
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 emits the high-order address
bytes during access to external memory and receives the high-order address bits and control signals
during program verification. Port 2 can sink/source three LS TTL inputs, and drive CMOS inputs without
external pull-ups.
P3.0–P3.7
36-43
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 can sink/source three LS
TTL inputs, and drive CMOS inputs without external pull-ups. Port 3 also serves the special functions
listed below:
36
I
RxD (P3.0): Serial input port
37
O
TxD (P3.1): Serial output port
38
I
INT0 (P3.2): External interrupt
39
I
INT1 (P3.3): External interrupt
40
I
T0 (P3.4): Timer 0 external input
41
I
T1 ( P3.5): Timer 1 external input
42
O
WR (P3.6): External data memory write strobe
43
O
RD (P3.7): External data memory read strobe
P4.0–P4.7
26-19
I/O
Port 4: Port 4 is a 8-bit (LCC) bidirectional I/O port with internal pull-ups. Port 4 can sink/source three
LS TTL inputs and drive CMOS inputs without external pull-ups.
P5.0–P5.7
44-51
I/O
Port 5: Port 5 is a 8-bit (LCC) bidirectional I/O port with internal pull-ups. Port 5 can sink/source three
LS TTL inputs and drive CMOS inputs without external pull-ups.
P6.0–P6.7
59-66
I/O
Port 6: Port 6 is a specialized 8-bit bidirectional I/O port with internal pull-ups. This special port can
sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 6 can be used in
a strobed or non-strobed mode of operation. Port 6 works in conjunction with four control pins that
serve the functions listed below:
ODS
55
I
ODS : Output data strobe
IDS
56
I
IDS: Input data strobe
BFLAG
57
I/O
BFLAG: Bidirectional I/O pin with internal pull-ups
AFLAG
58
I/O
AFLAG: Bidirectional I/O pin with internal pull-ups
RST
35
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An
internal pull-down resistor permits a power-on reset using only an external capacitor connected to V CC .
ALE/PROG
68
I/O
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during
an access to external memory. ALE is activated at a constant rate of 1/6 the oscillator frequency except
during an external data memory access, at which time one ALE is skipped. ALE can sink/source three
LS TTL inputs and drive CMOS inputs without external pull-ups. This pin is also the program pulse
during EPROM programming.
PSEN
67
O
Program Store Enable: The read strobe to external program memory. PSEN is activated twice each
machine cycle during fetches from e xterna l program memory. However, when executing out of external
program memor y, two activations of PSEN are skipped during each access to extern al program
memory. PSEN is not activated during fetches from internal program memory. PSEN can sink/source
eight LS TTL inputs and drive CMOS inputs without an external pull-up. This pin should be tied low
during programming.
EA/V PP
1
I
Instruction Execution Control/Programming Supply Voltage: When EA is held high, the C PU
executes out of internal program memory, unless the program co unter exceeds 0FFFH. When EA is
held low, the CPU executes out of external program memory. EA must never be allowed to float. This
pin also receives the 12.75V programming supply voltage (V PP ) during EPROM programming.
XTAL1
53
I
Crystal 1: Input to the inverting oscillator amplifier that forms the oscillator. This input receives the
external oscillator when an external oscillator is used.
XTAL2
52
O
Crystal 2: An output of the inverting amplifier that forms the oscillator. This pin should be floated when
an external oscillator is used.
1996 Aug 16
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