24C01.PDF

AT24C01

Features

Low Voltage and Standard Voltage Operation

5.0 (V CC = 4.5V to 5.5V)

2.7 (V CC = 2.7V to 5.5V)

2.5 (V CC = 2.5V to 5.5V)

1.8 (V CC = 1.8V to 5.5V)

Internally Organized 128 x 8

2-Wire Serial Interface

Bidirectional Data Transfer Protocol

2-Wire

Serial CMOS

E 2 PROM

100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility

4-Byte Page Write Mode

Self-Timed Write Cycle (10 ms max)

High Reliability

Endurance: 1 Million Cycles

Data Retention: 100 Years

Automotive Grade and Extended Temperature Devices Available

1K (128 x 8)

8-Pin PDIP and JEDEC SOIC Packages

Description

The AT24C01 provides 1024 bits of serial electrically erasable and programmable

read only memory (EEPROM) organized as 128 words of 8 bits each. The device is

optimized for use in many industrial and commercial applications where low power

and low voltage operation are essential. The AT24C01 is available in space saving

8-pin PDIP and 8-pin SOIC packages and is accessed via a 2-wire serial interface. In

addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V

(2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.

Pin Configurations

Pin Name

Function

AT24C01

No Connect

SDA

Serial Data

SCL

Serial Clock Input

Test

Test Input (GND or V CC )

8-Pin PDIP

8-Pin SOIC

0134B

2-3

Absolute Maximum Ratings*

Operating Temperature................... -55

C to +125

*NOTICE: Stresses beyond those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the

device at these or any other conditions beyond those indi-

cated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

Storage Temperature...................... -65

C to +150

Voltage on Any Pin

with Respect to Ground ..................... -0.1V to +7.0V

Maximum Operating Voltage ........................... 6.25V

DC Output Current ......................................... 5.0 mA

Block Diagram

Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive

edge clock data into each E 2 PROM device and negative

edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for se-

rial data transfer. This pin is open-drain driven and may be

wire-ORed with any number of other open-drain or open

collector devices.

Memory Organization

AT24C01, 1K SERIAL E 2 PROM: Internally organized

with 128 pages of 1-byte each. The 1K requires a 7 bit

data word address for random word addressing.

2-4

AT24C01

AT24C01

Pin Capacitance

Applicable over recommended operating range from T A = 25

C, f = 1.0 MHz, V CC = +1.8V.

Symbol

Test Condition

Max

Units

Conditions

C I/O

Input/Output Capacitance (SDA)

V I/O = 0V

C IN

Input Capacitance (A 0 , A 1 , A 2 , SCL)

V IN = 0V

DC Characteristics

Applicable over recommended operating range from: T AI = -40

C to +85

C, V CC = +1.8V to +5.5V, T AC = 0

C to +70

V CC = +1.8V to +5.5V (unless otherwise noted).

Symbol Parameter

Test Condition

Min

Typ

Max

Units

V CC1

Supply Voltage

1.8

5.5

V CC2

Supply Voltage

2.5

5.5

V CC3

Supply Voltage

2.7

5.5

V CC4

Supply Voltage

4.5

5.5

I CC

Supply Current V CC = 5.0V

READ at 100 kHz

0.4

1.0

I CC

Supply Current V CC = 5.0V

WRITE at 100 kHz

2.0

3.0

I SB1

Standby Current V CC = 1.8V

V IN = V CC or V SS

0.6

3.0

I SB2

Standby Current V CC = 2.5V

V IN = V CC or V SS

1.4

4.0

I SB3

Standby Current V CC = 2.7V

V IN = V CC or V SS

1.6

4.0

I SB4

Standby Current V CC = 5.0V

V IN = V CC or V SS

8.0

18.0

I LI

Input Leakage Current

V IN = V CC or V SS

0.10

3.0

I LO

Output Leakage Current

V OUT = V CC or V SS

0.05

3.0

V IL

Input Low Level (1)

-1.0

V CC x 0.3

V IH

Input High Level (1)

V CC x 0.7

V CC + 0.5

V OL2

Output Low Level V CC = 3.0V

I OL = 2.1 mA

0.4

V OL1

Output Low Level V CC = 1.8V

I OL = 0.15 mA

0.2

Note: 1. V IL min and V IH max are reference only and are not tested.

2-5

AC Characteristics

Applicable over recommended operating range from T A = -40

C to +85

C, V CC = +1.8V to +5.5V, CL = 1 TTL Gate and

100 pF (unless otherwise noted).

Symbol

Parameter

2.7-, 2.5-, 1.8-volt

5.0-volt

Min

Max

Min

Max

Units

f SCL

Clock Frequency, SCL

100

400

kHz

t LOW

Clock Pulse Width Low

4.7

1.2

t HIGH

Clock Pulse Width High

4.0

0.6

t I

Noise Suppression Time (1)

100

t AA

Clock Low to Data Out Valid

0.1

4.5

0.1

0.9

t BUF

Time the bus must be free before a new

transmission can start (1)

4.7

1.2

t HD.STA

Start Hold Time

4.0

0.6

t SU.STA

Start Set-up Time

4.7

0.6

t HD.DAT

Data In Hold Time

t SU.DAT

Data In Set-up Time

200

100

t R

Inputs Rise Time (1)

1.0

0.3

t F

Inputs Fall Time (1)

300

t SU.STO

Stop Set-up Time

4.7

0.6

t DH

Data Out Hold Time

100

Note: 1. This parameter is characterized and is not 100% tested.

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is nor-

mally pulled high with an external device. Data on the SDA

pin may change only during SCL low time periods (refer to

Data Validity timing diagram). Data changes during SCL

high periods will indicate a start or stop condition as de-

fined below.

START CONDITION: A high-to-low transition of SDA with

SCL high is a start condition which must precede any

other command (refer to Start and Stop Definition timing

diagram).

STOP CONDITION: A low-to-high transition of SDA with

SCL high is a stop condition which terminates all commu-

nications. After a read sequence, the stop command will

place the E 2 PROM in a standby power mode (refer to

Start and Stop Definition timing diagram).

ACKNOWLEDGE: All addresses and data words are se-

rially transmitted to and from the E 2 PROM in 8 bit words.

Any device on the system bus receiving data (when com-

municating with the E 2 PROM) must pull the SDA bus low

to acknowledge that it has successfully received each

word. This must happen during the ninth clock cycle after

each word received and after all other system devices

have freed the SDA bus. The E 2 PROM will likewise ac-

knowledge by pulling SDA low after receiving each ad-

dress or data word (refer to Acknowledge Response from

Receiver timing diagram).

STANDBY MODE: The AT24C01 features a low power

standby mode which is enabled: (a) upon power-up and

(b) after the receipt of the STOP bit and the completion of

any internal operations.

2-6

AT24C01

AT24C01

Bus Timing SCL: Serial Clock SDA: Serial Data I/O

Write Cycle Timing SCL: Serial Clock SDA: Serial Data I/O

Note: 1. The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

2-7

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