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The 68000's Instruction Set
W
e have included this appendix to save you the task of having to turn to secondary
material when writing 68000 assembly language programs. Since most
programmers are not interested in the encoding of instructions, details of
instruction encoding have been omitted (i.e., the actual op-code bit patterns).
Applications of some of the instructions have been provided to demonstrate how
they can be used in practice.
Instructions are listed by mnemonic in alphabetical order. The information
provided about each instruction is: its assembler syntax, its attributes (i.e., whether
it takes a byte, word, or longword operand), its description in words, the effect its
execution has on the condition codes, and the addressing modes it may take. The
effect of an instruction on the CCR is specified by the following codes:
U
The state of the bit is undefined (i.e., its value cannot be predicted)
-
The bit remains unchanged by the execution of the instruction
*
The bit is set or cleared according to the outcome of the instruction.
Unless an addressing mode is implicit (e.g.,
NOP
,
RESET
,
RTS
, etc.), the legal
source and destination addressing modes are specified by their assembly language
syntax. The following notation is used to describe the 68000's instruction set.
Data and address register direct.
Dn, An
Address register indirect.
(An)
Address register indirect with post-incrementing or pre-
decrementing.
(An)+, -(An)
Address register indirect with displacement, and address
register indirect with indexing and a displacement.
(d,An), (d,An,Xi)
Absolute addressing with a 16-bit or a 32-bit address.
ABS.W, ABS.L
Program counter relative addressing with a 16-bit offset,
or with an 8-bit offset plus the contents of an index
register.
(d,PC), (d,PC,Xi)
An immediate value (i.e., literal) which may be 16 or 32
bits, depending on the instruction.
imm
1
2
The 68000's Instruction Set
Two notations are employed for address register indirect addressing. The
notation originally used to indicate address register indirect addressing has been
superseded. However, the Teesside 68000 simulator supports only the older form.
Old notation
Current notation
d(An), d(An,Xi)
(d,An), (d,An,Xi)
d(PC), d(PC,Xi)
(d,PC), (d,PC,Xi)
ABCD
Add decimal with extend
Operation:
[destination]
10
¬
[source]
10
+ [destination]
10
+ [X]
Syntax:
ABCD Dy,Dx
ABCD -(Ay),-(Ax)
Attributes:
Size = byte
Description:
Add the source operand to the destination operand along with
the extend bit, and store the result in the destination location.
The addition is performed using BCD arithmetic. The only legal
addressing modes are data register direct and memory to memory
with address register indirect using pre-decrementing.
Application:
The
ABCD
instruction is used in chain arithmetic to add together
strings of BCD digits. Consider the addition of two nine-digit
numbers. Note that the strings are stored so that the least-
significant digit is at the high address.
LEA Number1,A0
A0 points at first string
LEA Number2,A1
A1 points at second string
MOVE #8,D0
Nine digits to add
MOVE #$04,CCR
Clear X-bit and Z-bit of the CCR
LOOP
ABCD -(A0),-(A1)
Add a pair of digits
DBRA D0,LOOP
Repeat until 9 digits added
Condition codes:
X N Z V C
* U * U *
The Z-bit is cleared if the result is non-zero, and left unchanged
otherwise. The Z-bit is normally set by the programmer before
the BCD operation, and can be used to test for zero after a chain
of multiple-precision operations. The C-bit is set if a decimal
carry is generated.
The 68000's Instruction Set
3
ADD
Add binary
Operation:
[destination]
¬
[source] + [destination]
Syntax:
ADD <ea>,Dn
ADD Dn,<ea>
Attributes:
Size = byte, word, longword
Description:
Add the source operand to the destination operand and store the
result in the destination location.
Condition codes:
X N Z V C
* * * * *
Source operand addressing modes
Destination operand addressing modes
ADDA
Add address
Operation:
[destination]
¬
[source] + [destination]
Syntax:
ADDA <ea>,An
Attributes:
Size = word, longword
Description:
Add the source operand to the destination address register and
store the result in the destination address register. The source is
sign-extended before it is added to the destination. For example,
if we execute
ADDA.W D3,A4
where A4 = 00000100
16
and D3.W =
8002
16
, the contents of D3 are sign-extended to FFFF8002
16
and
added to 00000100
16
to give FFFF8102
16
, which is stored in A4.
4
The 68000's Instruction Set
Application:
To add to the contents of an address register and not update the
CCR. Note that
ADDA.W
D0,A0
is the same as
LEA
(A0,D0.W),A0
.
Condition codes:
X N Z V C
- - - - -
An
ADDA
operation does not affect the state of the CCR.
Source operand addressing modes
ADDI
Add immediate
Operation:
[destination]
¬
<literal> + [destination]
Syntax:
ADDI #<data>,<ea>
Attributes:
Size = byte, word, longword
Description:
Add immediate data to the destination operand. Store the result
in the destination operand.
ADDI
can be used to add a literal
directly to a memory location. For example,
ADDI.W #$1234,$2000
has the effect [M(2000
16
)] ¬ [M(2000
16
)] + 1234
16
.
Condition codes:
X N Z V C
* * * * *
Destination operand addressing modes
ADDQ
Add quick
Operation:
[destination]
¬
<literal> + [destination]
Syntax:
ADDQ #<data>,<ea>
The 68000's Instruction Set
5
Sample syntax:
ADDQ #6,D3
Attributes:
Size = byte, word, longword
Description:
Add the immediate data to the contents of the destination operand.
The immediate data must be in the range 1 to 8. Word and
longword operations on address registers do not affect condition
codes. Note that a word operation on an address register affects
all bits of the register.
Application:
ADDQ
is used to add a small constant to the operand at the effective
address. Some assemblers permit you to write
ADD
and then choose
ADDQ
automatically if the constant is in the range 1 to 8.
Condition codes:
Z N Z V C
* * * * *
Note that the CCR is not updated if the destination operand is an
address register.
Destination operand addressing modes
ADDX
Add extended
Operation:
[destination]
¬
[source] + [destination] + [X]
Syntax:
ADDX Dy,Dx
ADDX -(Ay),-(Ax)
Attributes:
Size = byte, word, longword
Description:
Add the source operand to the destination operand along with
the extend bit, and store the result in the destination location.
The only legal addressing modes are data register direct and
memory to memory with address register indirect using pre-
decrementing.
Application:
The
ADDX
instruction is used in chain arithmetic to add together
strings of bytes (words or longwords). Consider the addition of
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