I2C_BUS_SPECIFICATION_2.pdf

THE I 2 C-BUS SPECIFICATION

VERSION 2.0

DECEMBER 1998

Philips Semiconductors

The I 2 C-bus speciﬁcation

CONTENTS

13.5.1 F/S-mode transfer in a

mixed-speed bus system

PREFACE

13.5.2 Hs-mode transfer in a

mixed-speed bus system

1.1

Version 1.0- 1992

1.2

Version 2.0- 1998

13.5.3 Timing requirements for the bridge in a

mixed-speed bus system

1.3

Purchase of Philips I 2 C-bus components

THE I 2 C-BUS BENEFITS DESIGNERS

AND MANUFACTURERS

10-BIT ADDRESSING

14.1

Definition of bits in the first two bytes

2.1

Designer benefits

14.2

Formats with 10-bit addresses

2.2

Manufacturer benefits

14.3

General call address and start byte

with 10-bit addressing

INTRODUCTION TO THE I 2 C-BUS

SPECIFICATION

ELECTRICAL SPECIFICATIONS

AND TIMING FOR I/O STAGES

AND BUS LINES

THE I 2 C-BUS CONCEPT

GENERAL CHARACTERISTICS

15.1

Standard- and Fast-mode devices

BIT TRANSFER

15.2

Hs-mode devices

6.1

Data validity

ELECTRICAL CONNECTIONS OF

I 2 C-BUS DEVICES TO THE BUS LINES

6.2

START and STOP conditions

TRANSFERRING DATA

16.1

Maximum and minimum values of

resistors R p and R s for Standard-mode

I 2 C-bus devices

7.1

Byte format

7.2

Acknowledge

ARBITRATION AND CLOCK

GENERATION

APPLICATION INFORMATION

17.1

Slope-controlled output stages of

Fast-mode I 2 C-bus devices

8.1

Synchronization

8.2

Arbitration

17.2

Switched pull-up circuit for Fast-

mode I 2 C-bus devices

8.3

Use of the clock synchronizing

mechanism as a handshake

17.3

Wiring pattern of the bus lines

17.4

Maximum and minimum values of

resistors R p and R s for Fast-mode

I 2 C-bus devices

FORMATS WITH 7-BIT ADDRESSES

7-BIT ADDRESSING

10.1

Definition of bits in the first byte

17.5

Maximum and minimum values of

resistors R p and R s for Hs-mode

I 2 C-bus devices

10.1.1 General call address

10.1.2 START byte

10.1.3 CBUS compatibility

BI-DIRECTIONAL LEVEL SHIFTER

FOR F/S-MODE I 2 C-BUS SYSTEMS

EXTENSIONS TO THE STANDARD-

MODE I 2 C-BUS SPECIFICATION

18.1

Connecting devices with different

logic levels

FAST-MODE

18.1.1 Operation of level shifter

Hs-MODE

13.1

High speed transfer

DEVELOPMENT TOOLS AVAILABLE

FROM PHILIPS

13.2

Serial data transfer format in Hs-mode

13.3

Switching from F/S- to Hs-mode and back

SUPPORT LITERATURE

13.4Hs-mode devices at lower speed modes24

13.5

Mixed speed modes on one serial

bus system

Philips Semiconductors

The I 2 C-bus speciﬁcation

1 PREFACE

1.2 Version 2.0 - 1998

The I 2 C-bus has become a de facto world standard that is

now implemented in over 1000 different ICs and licensed

to more than 50 companies. Many of today’s applications,

however, require higher bus speeds and lower supply

voltages. This updated version of the I 2 C-bus specification

meets those requirements and includes the following

modifications:

1.1 Version 1.0 - 1992

This version of the 1992 I 2 C-bus specification includes the

following modifications:

Programming of a slave address by software has been

omitted. The realization of this feature is rather

complicated and has not been used.

The “low-speed mode” has been omitted. This mode is,

in fact, a subset of the total I 2 C-bus specification and

need not be specified explicitly.

The High-speed mode (Hs-mode) is added. This allows

an increase in the bit rate up to 3.4 Mbit/s. Hs-mode

devices can be mixed with Fast- and Standard-mode

devices on the one I 2 C-bus system with bit rates from 0

to 3.4 Mbit/s.

The Fast-mode is added. This allows a fourfold increase

of the bit rate up to 400 kbit/s. Fast-mode devices are

downwards compatible i.e. they can be used in a 0 to

100 kbit/s I 2 C-bus system.

The low output level and hysteresis of devices with a

supply voltage of 2 V and below has been adapted to

meet the required noise margins and to remain

compatible with higher supply voltage devices.

10-bit addressing is added. This allows 1024 additional

slave addresses.

Slope control and input filtering for Fast-mode devices is

specified to improve the EMC behaviour.

NOTE: Neither the 100 kbit/s I 2 C-bus system nor the

100 kbit/s devices have been changed.

The 0.6 V at 6 mA requirement for the output stages of

Fast-mode devices has been omitted.

The fixed input levels for new devices are replaced by

bus voltage-related levels.

Application information for bi-directional level shifter is

added.

1.3

Purchase of Philips I 2 C-bus components

Purchase of Philips I 2 C components conveys a license under the Philips’ I 2 C patent to use the

components in the I 2 C system provided the system conforms to the I 2 C specification defined by

Philips.

Philips Semiconductors

The I 2 C-bus speciﬁcation

2 THE I 2 C-BUS BENEFITS DESIGNERS AND

MANUFACTURERS

In consumer electronics, telecommunications and

industrial electronics, there are often many similarities

between seemingly unrelated designs. For example,

nearly every system includes:

The number of ICs that can be connected to the same

bus is limited only by a maximum bus capacitance of

400 pF.

Figure 1 shows two examples of I 2 C-bus applications.

Some intelligent control, usually a single-chip

microcontroller

2.1 Designer beneﬁts

I 2 C-bus compatible ICs allow a system design to rapidly

progress directly from a functional block diagram to a

prototype. Moreover, since they ‘clip’ directly onto the

I 2 C-bus without any additional external interfacing, they

allow a prototype system to be modified or upgraded

simply by ‘clipping’ or ‘unclipping’ ICs to or from the bus.

Here are some of the features of I 2 C-bus compatible ICs

which are particularly attractive to designers:

General-purpose circuits like LCD drivers, remote I/O

ports, RAM, EEPROM, or data converters

Application-oriented circuits such as digital tuning and

signal processing circuits for radio and video systems,

or DTMF generators for telephones with tone dialling.

To exploit these similarities to the benefit of both systems

designers and equipment manufacturers, as well as to

maximize hardware efficiency and circuit simplicity, Philips

developed a simple bi-directional 2-wire bus for efficient

inter-IC control. This bus is called the Inter IC or I 2 C-bus.

At present, Philips’ IC range includes more than 150

CMOS and bipolar I 2 C-bus compatible types for

performing functions in all three of the previously

mentioned categories. All I 2 C-bus compatible devices

incorporate an on-chip interface which allows them to

communicate directly with each other via the I 2 C-bus. This

design concept solves the many interfacing problems

encountered when designing digital control circuits.

Here are some of the features of the I 2 C-bus:

Functional blocks on the block diagram correspond with

the actual ICs; designs proceed rapidly from block

diagram to final schematic.

No need to design bus interfaces because the I 2 C-bus

interface is already integrated on-chip.

Integrated addressing and data-transfer protocol allow

systems to be completely software-defined

The same IC types can often be used in many different

applications

Design-time reduces as designers quickly become

familiar with the frequently used functional blocks

represented by I 2 C-bus compatible ICs

Only two bus lines are required; a serial data line (SDA)

and a serial clock line (SCL)

ICs can be added to or removed from a system without

affecting any other circuits on the bus

Fault diagnosis and debugging are simple; malfunctions

can be immediately traced

Each device connected to the bus is software

addressable by a unique address and simple

master/slave relationships exist at all times; masters can

operate as master-transmitters or as master-receivers

Software development time can be reduced by

assembling a library of reusable software modules.

It’s a true multi-master bus including collision detection

and arbitration to prevent data corruption if two or more

masters simultaneously initiate data transfer

In addition to these advantages, the CMOS ICs in the

I 2 C-bus compatible range offer designers special features

which are particularly attractive for portable equipment and

battery-backed systems.

Serial, 8-bit oriented, bi-directional data transfers can be

made at up to 100 kbit/s in the Standard-mode, up to

400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the

High-speed mode

They all have:

Extremely low current consumption

High noise immunity

On-chip filtering rejects spikes on the bus data line to

preserve data integrity

Wide supply voltage range

Wide operating temperature range.

Philips Semiconductors

The I 2 C-bus speciﬁcation

handbook, full pagewidth

SDA SCL

MICRO-

CONTROLLER

PCB83C528

PLL

SYNTHESIZER

TSA5512

NON-VOLATILE

MEMORY

PCF8582E

M/S COLOUR

DECODER

TDA9160A

STEREO / DUAL

SOUND

DECODER

TDA9840

SDA SCL

PICTURE

SIGNAL

IMPROVEMENT

DTMF

GENERATOR

TDA4670

PCD3311

HI-FI

AUDIO

PROCESSOR

LINE

INTERFACE

TDA9860

PCA1070

VIDEO

PROCESSOR

ADPCM

TDA4685

PCD5032

SINGLE-CHIP

TEXT

BURST MODE

CONTROLLER

SAA52XX

PCD5042

ON-SCREEN

DISPLAY

MICRO-

CONTROLLER

PCA8510

P80CLXXX

MSB575

(a)

(b)

Fig.1 Two examples of I 2 C-bus applications: (a) a high performance highly-integrated TV set

(b) DECT cordless phone base-station.

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