Receiver with LO at working frequency - DR2C from 30 KHz to 50 MHz.pdf

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Monoband SDR HF S/H Sample and Hold Receiver With LO at working frequency DR2C from 10 kHz to 50 MHz
Monoband SDR HF S/H Sample and Hold Receiver with LO at working
frequency - DR2C from 30 KHz to 50 MHz-Make it Simple as Possible with
Outstanding performances
Dipl. Ing . Tasić Siniša –Tasa YU1LM/QRP
All rights reserved, project is free for personal use only
Many HAMs all over the world built my SDR S/H receivers DR1, DR2, DR2A,
DR1A…. you can see some photos on my sites and I can noticed that they are all satisfied with
results . Simple constructions with cheap classic components working really very well. Also I
find at INTERNET that some solutions from my receivers/transmitters are used in some new
SDR projects.
I made local demonstrations of my SDR projects here in Belgrade. Presentation was for
KKE club in YU1EXY club. Audience was very surprised with very good received demodulated
signal quality, crisp and clear sound like HI-FI (high fidelity) not common for the most
commercial RIGs. SDR possibilities such as adjustable selectivity, noise reduction, NB noise
blanker; waterfall… was discovery for most of them. Local HAMs first excitements with new
SDR techniques ware replaced with some disappointment because most HAMs like to tune LO
(local oscillator) all over the working band and they are not satisfied with +/- 20 KHz with fixed
LO. Also some easy obtainable XTAL quartz or OSC are not in very interesting parts of HF
HAM bands. It is not easy build or it wasn’t easy to build ever stabile LO at 120 MHz for 30
MHz or 56 MHz for 14 MHz. DDS LO is not easy to build for most builders also, a lot of
reasons: hard to find IC-s, expensive and SMD components, needs for precise PCB for IC
soldering…. Other solutions like PLLs are not so easy for realization also. In meanwhile I made
some experiments how to simplify my simple SDR construction with even simpler and cheaper
design. I decided to try new SDR design with some other IC and make SDR closer to HAM
which like to try new technique with less problems cased with high LO frequencies. Result is HF
SDR S/H receiver DR3X one LO or XTAL enable 3 bands harmonically related receiving.
I also decided to try some not optimum technique obtaining I/Q 90 DEG branches for
driving CMOS switches ref2 instead better technique with double D FF 74AC74 for max input
frequency . Advantage of using 50/50 % duty cycle technique I explained in previously articles.
Advantage is evident very much in my SDR transmission projects DT1, DT2 and DT2A. In
receivers this 50/50 % ratio is not so important like for the transmission except for increasing
max input frequencies with used hardware realization.
Here is a new one monoband HF SDR S/H receiver called DR2C with LO at receiving
frequency from 30 KHz to 50 MHz. 90 DEG shift is obtaining with RC LP (low pass) network.
What is very important for design it is gate output impedance which is driving RC networks is
small as possible. At that way its output impedance influence to 90 deg phase shift is small as
possible. Because of that I paralleled 3 inverters 74HC04 to decrease output impedance. It is
important that is at output first inverter duty cycle close to optimum 50/50 % also. This is easy
obtain able with clear sinusoidal drive signal with high amplitude 1 Vp-p or more for example.
This solution is frequency depending design Exactly 90 deg shift is only at one frequency but for
some practical used bandwidth it is OK. This mean that is possible satisfactory receive with
relative good image rejection almost in all HAM bands to 50 MHz .Change inside most band is
under 1 DEG. This is very important if you like to try SDR technology in commercial RIG as
new IF . Design is also temperature sensitive .There is some change in 1 or 0 logical levels with
bigger temperature change for CMOS ICs. In normal temperature range or room temperature
work phase change with temperature change is very small. To reduce this problem little help is
10 K resistor at input of invertors.
Solution for phase shift with increasing R have big disadvantage for higher HF
frequencies shift capacitor C became small and close to parasitic C inside IC invertors. In
schematic I proposed some values for all HAM bands to 50-60 MHz which is close to the upper
limit for IC 74 HC 4053 but it is possible other different components combination also.
Components placement is done first for all 3 possibilities together XTAL quartz OSC, DIL OSC
and external LO connection. Individual. XTAL quartz OSC is working to 30 MHz this
schematics will not working on overtone quartz frequencies and frequencies over 30 MHz! For
the receiving frequencies over 30 MHz LO source is possible DIL oscillator or some external
oscillator working to 50 MHz with levels min 0 dBm.
This design is ideal for build in inside some RX to obtain I/Q outputs for SDR sound card DSP
processing. Carrier USB/LSB quartz can be easily move up 3-10 kHz with help C23. This mean
that is LF IF in region 3-10 KHz that is enough to use I/Q with better success than ordinary AF
sound card processing. Value for capacitor C23 is necessary to determine and obtain optimum
max frequency shift and stabile oscillation at the same time.
RC Shift network are not shifting 90 DEG initially but shift is around 66 DEG. Signal
which is coming to the inverter gate is not sinusoidal wave signal but close to saw signal .We
have a DC level for changing inverter levels from 1 to 0 or vice versa also. Together we obtain
90 DEG. See simulation curves are done for 14 MHz and 50 MHz bands.
PORT
P=1
Z=10 Ohm
RES
ID=R1
R=100 Ohm
PORT
P=1
Z=10 Ohm
RES
ID=R1
R=100 Ohm
CAP
ID=C1
C=270 pF
PORT
P=2
Z=1e4 Ohm
CAP
ID=C1
C=68 pF
PORT
P=2
Z=1e4 Ohm
Values for phase sift network on 14 MHz and 50 MHz bands
303575975.009.png
50.1 MHz
-8.173 dB
TRANS
52.04 MHz
-8.453 dB
0
-20
Ang(VSG(2,1)) (Deg)
DR2C PHASE SHIFT
DB(|VSG(2,1)|)
DR2C PHASE SHIFT
-40
-60
50.1 MHz
-66.76 Deg
52.03 MHz
-67.54 Deg
-80
40
45
50
55
60
Frequency (MHz)
0
13.996 MHz
-8.945 dB
TRANS
14.353 MHz
-9.135 dB
-20
Ang(VSG(2,1)) (Deg)
DR2C PHASE SHIFT
-40
DB(|VSG(2,1)|)
DR2C PHASE SHIFT
13.995 MHz
-68.84 Deg
14.353 MHz
-69.32 Deg
-60
-80
12
13
14
15
16
Frequency (MHz)
Phase shift simulation for both bands to notice in band phase change
303575975.010.png 303575975.011.png 303575975.012.png 303575975.001.png 303575975.002.png 303575975.003.png 303575975.004.png 303575975.005.png 303575975.006.png
Parts placement for DIL oscillator
Parts placement for external oscillator
303575975.007.png
303575975.008.png
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