TL061,2,4,A,B.pdf

SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

Very Low Power Consumption

Output Short-Circuit Protection

Typical Supply Current . . . 200

High Input Impedance . . . JFET-Input Stage

(Per Amplifier)

Internal Frequency Compensation

Wide Common-Mode and Differential

Voltage Ranges

Latch-Up-Free Operation

High Slew Rate . . . 3.5 V/

s Typ

Low Input Bias and Offset Currents

Common-Mode Input Voltage Range

Includes V CC+

TL061, TL061A . . . D, P, OR PS PACKAGE

TL061B ...P PACKAGE

(TOP VIEW)

TL062 . . . D, JG, P, PS, OR PW PACKAGE

TL062A . . . D, P, OR PS PACKAGE

TL062B ...D OR P PACKAGE

(TOP VIEW)

OFFSET N1

IN−

IN+

V CC−

V CC+

OUT

OFFSET N2

1OUT

1IN−

1IN+

V CC−

V CC+

2OUT

2IN−

2IN+

TL062 . . . FK PACKAGE

(TOP VIEW)

TL064 . . . FK PACKAGE

(TOP VIEW)

TL064 . . . D, J, N, NS, PW, OR W PACKAGE

TL064A, TL064B ...D OR N PACKAGE

(TOP VIEW)

1OUT

1IN−

1IN+

V CC+

2IN+

2IN−

2OUT

4OUT

4IN−

4IN+

V CC−

3IN+

3IN−

3OUT

20 19

3212019

2OUT

2IN−

1IN−

1IN+

4IN+

V CC−

3IN+

1IN+

V CC+

2IN+

910111213

NC − No internal connection

description/ordering information

The JFET-input operational amplifiers of the TL06_ series are designed as low-power versions of the

TL08_ series amplifiers. They feature high input impedance, wide bandwidth, high slew rate, and low input offset

and input bias currents. The TL06_ series features the same terminal assignments as the TL07_ and

TL08_ series. Each of these JFET-input operational amplifiers incorporates well-matched, high-voltage JFET

and bipolar transistors in an integrated circuit.

The C-suffix devices are characterized for operation from 0

C to 70

C. The I-suffix devices are characterized

for operation from −40

C to 85

C, and the M-suffix devices are characterized for operation over the full military

temperature range of −55

C to 125

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2004, Texas Instruments Incorporated

•

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

description/ordering information (continued)

ORDERING INFORMATION

V IO MAX

AT 25

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PACKAGE †

T A

TL061CP

PDIP (P)

Tube of 50

TL062CP

PDIP (N)

Tube of 25

TL064CN

Tube of 75

TL061CD

TL061C

Reel of 2500

TL061CDR

Tube of 75

TL062CD

SOIC (D)

TL062C

Reel of 2500

TL062CDR

Tube of 50

TL064CD

15 mV

TL064C

Reel of 2500

TL064CDR

TL061CPSR

T061

SOP (PS)

Reel of 2000

TL062CPSR

T062

SOP (NS)

Reel of 2000

TL064CNSR

TL064

Tube of 150

TL062CPW

T062

Reel of 2000

TL062CPWR

TSSOP (PW)

Tube of 90

TL064CPW

T064

Reel of 2000

TL064CPWR

TL061ACP

C to 70

PDIP (P)

Tube of 50

TL062ACP

PDIP (N)

Tube of 25

TL064ACN

Tube of 75

TL061ACD

061AC

Reel of 2500

TL061ACDR

Tube of 75

TL062ACD

6 mV

SOIC (D)

062AC

Reel of 2500

TL062ACDR

Tube of 50

TL064ACD

TL064AC

Reel of 2500

TL064ACDR

TL061ACPSR

T061A

SOP (PS)

Reel of 2000

TL062ACPSR

T062A

TL061BCP

PDIP (P)

Tube of 50

TL062BCP

PDIP (N)

Tube of 25

TL064BCN

3 mV

Tube of 75

TL062BCD

3 mV

062BC

Reel of 2500

TL062BCDR

SOIC (D)

Tube of 50

TL064BCD

TL064BC

Reel of 2500

TL064BCDR

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

•

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

description/ordering information (continued)

ORDERING INFORMATION (continued)

V IO MAX

AT 25

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PACKAGE †

T A

TL061IP

PDIP (P)

Tube of 50

TL062IP

PDIP (N)

Tube of 25

TL064IN

Tube of 75

TL061ID

TL061I

Reel of 2000

TL061IDR

−40 ° C to 85 ° C

6 mV

Tube of 75

TL062ID

SOIC (D)

TL062I

Reel of 2000

TL062IDR

Tube of 50

TL064ID

TL064I

Reel of 2500

TL064IDR

TSSOP (PW)

Reel of 2000

TL062IPWR

TL062I

CDIP (JG)

Tube of 50

TL062MJG

6 mV

LCCC (FK)

Tube of 55

TL062MFK

−55 ° C to 125 ° C

CDIP (J)

Tube of 25

TL064MJ

−55 C to 125 C

9 mV

CFP (W)

Tube of 150

TL064MW

9 mV

LCCC (FK) Tube of 55 TL064MFK TL064MFK

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

•

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

symbol (each amplifier)

−

IN+

IN−

OUT

OFFSET N1

Offset Null/Compensation

TL061 Only

OFFSET N2

schematic (each amplifier)

V CC+

IN+

50 Ω

IN−

100 Ω

OFFSET N1

OFFSET N2

OUT

V CC−

TL061 Only

C1 = 10 pF on TL061, TL062, and TL064

Component values shown are nominal.

•

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

absolute maximum ratings over operating free-air temperature range (unless otherwise noted) †

TL06_C

TL06_AC

TL06_BC

TL06_I

TL06_M

UNIT

Supply voltage, V CC+ (see Note 1)

Supply voltage, V CC− (see Note 1)

−18

Differential input voltage, V ID (see Note 2)

Input voltage, V I (see Notes 1 and 3)

± 15

Duration of output short circuit (see Note 4)

Unlimited

D (8-pin) package

D (14-pin) package

N package

NS package

Package thermal impedance, θ JA (see Notes 5 and 6)

° C/W

P package

Package thermal impedance, JA (see Notes 5 and 6)

C/W

PS package

PW (8-pin) package

149

PW (14-pin)

package

113

FK package

5.61

J package

15.05

Package thermal impedance, θ JC (see Notes 7 and 8)

° C/W

JG package

14.5

W package

14.65

Operating virtual junction temperature, T J

150

° C

Case temperature for 60 seconds

FK package

260

Lead temperature 1,6 mm (1/16 inch) from case for 60

J, JG, U, or

Lead temperature 1,6 mm (1/16 inch) from case for 60

seconds

J, JG, U, or

W package

300

° C

Lead temperature 1,6 mm (1/6 inch) from case for 10

D, N, NS, P, PS,

Lead temperature 1,6 mm (1/6 inch) from case for 10

seconds

D, N, NS, P, PS,

or PW package

260

° C

Storage temperature range, T stg −65 to 150 −65 to 150 −65 to 150 ° C

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

All voltage values except differential voltages are with respect to the midpoint between V CC+ and V CC− .

Differential voltages are at IN+ with respect to IN−.

The magnitude of the input voltage should never exceed the magnitude of the supply voltage or 15 V, whichever is less.

The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the

dissipation rating is not exceeded.

Maximum power dissipation is a function of T J (max),

θ JA , and T A . The maximum allowable power dissipation at any allowable

ambient temperature is P D = (T J (max) − T A )/

θ JA . Operating at the absolute maximum T J of 150

C can affect reliability.

The package thermal impedance is calculated in accordance with JESD 51-7.

Maximum power dissipation is a function of T J (max),

θ JC , and T C . The maximum allowable power dissipation at any allowable case

temperature is P D = (T J (max) − T C )/

θ JC . Operating at the absolute maximum T J of 150

C can affect reliability.

The package thermal impedance is calculated in accordance with MIL-STD-883.

•

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

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